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Silicon Revision Functional Differences and Enhancements
1.2 Silicon Revision Functional Differences and Enhancements
This section describes the differences in functionality among different silicon revisions of AM335x.
Enhancements introduced in silicon revisions are also described. For a description of silicon bugs that
were fixed in later revisions of the device, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon
Errata (literature number SPRZ360). Errata items that were fixed may or may not show up in this section.
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes
See Section 8.1.4.5, Wakeup Sources/Events.
PG1.0: RTC alarm will not wake up device from DeepSleep0.
PG2.x: RTC alarm was added as a wake-up source from DeepSleep modes.
1.2.2 Changed BOOTP Identifier
See Section 26.1.8.4.2, BOOTP (RFC 951) and Errata Advisory 1.0.8.
PG1.0: BOOTP Identifier string is "DM814x ROM v1.0".
PG2.x: BOOTP Identifier string is "AM335x ROM".
1.2.3 Changed Product String in USB Descriptor
See Section 26.1.8.6.1.2, Enumeration Descriptors.
PG1.0: Product string in USB descriptor is "Subarctic".
PG2.x: Product string in USB descriptor is "AM335x USB".
1.2.4 Added DPLL Power Switch Control and Status Registers
See Section 9.3.14, dpll_pwr_sw_status Register, and Section 9.3.76, dpll_pwr_sw_ctrl Register.
PG1.0: DPLL Power Switch Control and Status registers do not exist.
PG2.x: Added DPLL Power Switch Control and DPLL Power Switch Status registers in the Control Module
to facilitate power optimization.
1.2.5 Added Control for CORE SRAM LDO Retention Mode
See newly added SMA2 register, Section 9.3.78.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.VSLDO_CORE_AUTO_RAMP_EN.
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing
See newly added SMA2 register, Section 9.3.78.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.RMII2_CRS_DV_MODE_SEL.
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)
See Section 6.3, ARM Cortex-A8 Interrupts and Errata Advisory 1.0.6.
PG1.0: nNMI input signal is active high.
PG2.x: nNMI input signal is active low.
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SPRUH73H–October 2011–Revised April 2013 Introduction
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