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McSPI Registers
24.4.1.2 McSPI System Configuration Register (MCSPI_SYSCONFIG)
The McSPI system configuration register (MCSPI_SYSCONFIG) allows control of various parameters of
the module interface. It is not sensitive to software reset. The MCSPI_SYSCONFIG is shown in Figure 24-
27 and described in Table 24-12.
Figure 24-27. McSPI System Configuration Register (MCSPI_SYSCONFIG)
31 16
Reserved
R/W-0
15 10 9 8
Reserved CLOCKACTIVITY
R/W-0 R/W-0
7 5 4 3 2 1 0
Reserved SIDLEMODE Reserved SOFTRESET AUTOIDLE
R/W-0 R/W-2h R R/W-0 R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 24-12. McSPI System Configuration Register (MCSPI_SYSCONFIG) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reads returns 0
9-8 CLOCKACTIVITY Clocks activity during wake-up mode period.
0 OCP and Functional clocks may be switched off.
1h OCP clock is maintained. Functional clock may be switched-off.
2h Functional clock is maintained. OCP clock may be switched-off.
3h OCP and Functional clocks are maintained.
7-5 Reserved 0 Reads returns 0
4-3 SIDLEMODE Power management
0 If an idle request is detected, the McSPI acknowledges it unconditionally and goes in
Inactive mode. Interrupt, DMA requests are unconditionally de-asserted.
1h If an idle request is detected, the request is ignored and keeps on behaving normally.
2h Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle
requests, depending on the IP module's internal requirements.
3h Reserved
2 Reserved 0 Reserved
1 SOFTRESET Software reset. During reads it always returns 0.
0 (write) Normal mode
1 (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the
hardware.
0 AUTOIDLE Internal OCP Clock gating strategy
0 OCP clock is free-running
1 Automatic OCP clock gating strategy is applied, based on the OCP interface activity
4035
SPRUH73H–October 2011–Revised April 2013 Multichannel Serial Port Interface (McSPI)
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