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CONTROL_MODULE Registers
9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h]
dcan_raminit is shown in Figure 9-32 and described in Table 9-39.
Figure 9-32. dcan_raminit Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved dcan1_raminit_done dcan0_raminit_done
R-0h R/W1toClr R/W1toClr
7 6 5 4 3 2 1 0
Reserved dcan1_raminit_start dcan0_raminit_start
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-39. dcan_raminit Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9 dcan1_raminit_done R/W1toClr 0h 0: DCAN1 RAM Initialization NOT complete
1: DCAN1 RAM Initialization complete
8 dcan0_raminit_done R/W1toClr 0h 0: DCAN0 RAM Initialization NOT complete
1: DCAN0 RAM Initialization complete
7-2 Reserved R 0h
1 dcan1_raminit_start R/W 0h A transition from 0 to 1 will start DCAN1 RAM initialization sequence.
0 dcan0_raminit_start R/W 0h A transition from 0 to 1 will start DCAN0 RAM initialization sequence.
793
SPRUH73H–October 2011–Revised April 2013 Control Module
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