www.ti.com
DCAN Registers
23.4.21 INTPND34 Register (offset = B4h) [reset = 0h]
INTPND34 is shown in Figure 23-39 and described in Table 23-34.
These registers hold the IntPnd bits of the implemented message objects. By reading out these bits, the
CPU can check for pending interrupts in the message objects. The IntPnd bit of a specific message object
can be set/reset by the CPU via the IF1/IF2 interface register sets, or by the message handler after a
reception or a successful transmission.
Figure 23-39. INTPND34 Register
31 30 29 28 27 26 25 24
IntPnd[64:49]
R-0h
23 22 21 20 19 18 17 16
IntPnd[64:49]
R-0h
15 14 13 12 11 10 9 8
IntPnd[48:33]
R-0h
7 6 5 4 3 2 1 0
IntPnd[48:33]
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-34. INTPND34 Register Field Descriptions
Bit Field Type Reset Description
31-16 IntPnd[64:49] R 0h
Interrupt Pending Bits (for all message objects)
0x0 = This message object is not the source of an interrupt.
0x1 = This message object is the source of an interrupt.
15-0 IntPnd[48:33] R 0h
Interrupt Pending Bits (for all message objects)
0x0 = This message object is not the source of an interrupt.
0x1 = This message object is the source of an interrupt.
3947
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
