Enhanced Capture (eCAP) Module
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15.3.4 Registers
All 32-bit registers are aligned on even address boundaries and are organized in little-endian mode. The
16 least-significant bits of a 32-bit register are located on lowest address (even address).
NOTE: In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the
shadow registers CAP3/CAP4 invokes the shadow mode.
15.3.4.1 ECAP Registers
Table 15-108 lists the memory-mapped registers for the ECAP. All register offset addresses not listed in
Table 15-108 should be considered as reserved locations and the register contents should not be
modified.
Table 15-108. ECAP REGISTERS
Offset Acronym Register Name Section
0h TSCTR Time-Stamp Counter Register Section 15.3.4.1.1
4h CTRPHS Counter Phase Offset Value Register Section 15.3.4.1.2
8h CAP1 Capture 1 Register Section 15.3.4.1.3
Ch CAP2 Capture 2 Register Section 15.3.4.1.4
10h CAP3 Capture 3 Register Section 15.3.4.1.5
14h CAP4 Capture 4 Register Section 15.3.4.1.6
28h ECCTL1 Capture Control Register 1 Section 15.3.4.1.7
2Ah ECCTL2 Capture Control Register 2 Section 15.3.4.1.8
2Ch ECEINT Capture Interrupt Enable Register Section 15.3.4.1.9
2Eh ECFLG Capture Interrupt Flag Register Section 15.3.4.1.10
30h ECCLR Capture Interrupt Clear Register Section 15.3.4.1.11
32h ECFRC Capture Interrupt Force Register Section 15.3.4.1.12
5Ch REVID Revision ID Register Section 15.3.4.1.13
1634
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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