Ethernet Subsystem Registers
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14.5.2.39 RX5_PENDTHRESH Register (offset = D4h) [reset = 0h]
RX5_PENDTHRESH is shown in Figure 14-67 and described in Table 14-78.
CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 5
Figure 14-67. RX5_PENDTHRESH Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
RX_PENDTHRESH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-78. RX5_PENDTHRESH Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 RX_PENDTHRESH R/W 0h Rx Flow Threshold - This field contains the threshold value for
issuing receive threshold pending interrupts (when enabled).
1298
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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