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EDMA3 Registers
11.4.1.1.5 QDMA Channel Map n Registers (QCHMAPn)
Each QDMA channel in EDMA3CC can be associated with any PaRAM set available on the device.
Furthermore, the specific trigger word (0-7) of the PaRAM set can be programmed. The PaRAM set
association and trigger word for every QDMA channel register is configurable using the QDMA channel
map n register (QCHMAPn).
The QCHMAPn is shown in Figure 11-46 and described in Table 11-30.
NOTE: At reset the QDMA channel map registers for all QDMA channels point to PaRAM set 0. If an
application makes use of both a DMA channel that points to PaRAM set 0 and any QDMA
channels, ensure that QCHMAPn is programmed appropriately to point to a different PaRAM
entry.
Figure 11-46. QDMA Channel Map n Registers (QCHMAPn)
31 16
Reserved
R-0
15 14 13 5 4 2 1 0
Reserved PAENTRY TRWORD Reserved
R-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-30. QDMA Channel Map n Registers (QCHMAPn) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do
so may result in undefined behavior.
13-5 PAENTRY 0-1FFh PAENTRY points to the PaRAM set number for QDMA channel n.
0-FFh Parameter entry 0 through 255.
100h-1FFh Reserved.
4-2 TRWORD 0-7h Points to the specific trigger word of the PaRAM set defined by PAENTRY. A write to the trigger
word results in a QDMA event being recognized.
1-0 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do
so may result in undefined behavior.
947
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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