Power, Reset, and Clock Management
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8.1.12 Clock Module Registers
8.1.12.1 CM_PER Registers
Table 8-29 lists the memory-mapped registers for the CM_PER. All register offset addresses not listed in
Table 8-29 should be considered as reserved locations and the register contents should not be modified.
Table 8-29. CM_PER REGISTERS
Offset Acronym Register Name Section
0h CM_PER_L4LS_CLKSTCTRL Section 8.1.12.1.1
4h CM_PER_L3S_CLKSTCTRL Section 8.1.12.1.2
8h CM_PER_L4FW_CLKSTCTRL Section 8.1.12.1.3
Ch CM_PER_L3_CLKSTCTRL Section 8.1.12.1.4
14h CM_PER_CPGMAC0_CLKCTRL Section 8.1.12.1.5
18h CM_PER_LCDC_CLKCTRL Section 8.1.12.1.6
1Ch CM_PER_USB0_CLKCTRL Section 8.1.12.1.7
24h CM_PER_TPTC0_CLKCTRL Section 8.1.12.1.8
28h CM_PER_EMIF_CLKCTRL Section 8.1.12.1.9
2Ch CM_PER_OCMCRAM_CLKCTRL Section 8.1.12.1.10
30h CM_PER_GPMC_CLKCTRL Section 8.1.12.1.11
34h CM_PER_MCASP0_CLKCTRL Section 8.1.12.1.12
38h CM_PER_UART5_CLKCTRL Section 8.1.12.1.13
3Ch CM_PER_MMC0_CLKCTRL Section 8.1.12.1.14
40h CM_PER_ELM_CLKCTRL Section 8.1.12.1.15
44h CM_PER_I2C2_CLKCTRL Section 8.1.12.1.16
48h CM_PER_I2C1_CLKCTRL Section 8.1.12.1.17
4Ch CM_PER_SPI0_CLKCTRL Section 8.1.12.1.18
50h CM_PER_SPI1_CLKCTRL Section 8.1.12.1.19
60h CM_PER_L4LS_CLKCTRL Section 8.1.12.1.20
64h CM_PER_L4FW_CLKCTRL Section 8.1.12.1.21
68h CM_PER_MCASP1_CLKCTRL Section 8.1.12.1.22
6Ch CM_PER_UART1_CLKCTRL Section 8.1.12.1.23
70h CM_PER_UART2_CLKCTRL Section 8.1.12.1.24
74h CM_PER_UART3_CLKCTRL Section 8.1.12.1.25
78h CM_PER_UART4_CLKCTRL Section 8.1.12.1.26
7Ch CM_PER_TIMER7_CLKCTRL Section 8.1.12.1.27
80h CM_PER_TIMER2_CLKCTRL Section 8.1.12.1.28
84h CM_PER_TIMER3_CLKCTRL Section 8.1.12.1.29
88h CM_PER_TIMER4_CLKCTRL Section 8.1.12.1.30
ACh CM_PER_GPIO1_CLKCTRL Section 8.1.12.1.31
B0h CM_PER_GPIO2_CLKCTRL Section 8.1.12.1.32
B4h CM_PER_GPIO3_CLKCTRL Section 8.1.12.1.33
BCh CM_PER_TPCC_CLKCTRL Section 8.1.12.1.34
C0h CM_PER_DCAN0_CLKCTRL Section 8.1.12.1.35
C4h CM_PER_DCAN1_CLKCTRL Section 8.1.12.1.36
CCh CM_PER_EPWMSS1_CLKCTRL Section 8.1.12.1.37
D0h CM_PER_EMIF_FW_CLKCTRL Section 8.1.12.1.38
D4h CM_PER_EPWMSS0_CLKCTRL Section 8.1.12.1.39
D8h CM_PER_EPWMSS2_CLKCTRL Section 8.1.12.1.40
DCh CM_PER_L3_INSTR_CLKCTRL Section 8.1.12.1.41
E0h CM_PER_L3_CLKCTRL Section 8.1.12.1.42
548
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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