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Power, Reset, and Clock Management
Table 8-29. CM_PER REGISTERS (continued)
Offset Acronym Register Name Section
E4h CM_PER_IEEE5000_CLKCTRL Section 8.1.12.1.43
E8h CM_PER_PRU_ICSS_CLKCTRL Section 8.1.12.1.44
ECh CM_PER_TIMER5_CLKCTRL Section 8.1.12.1.45
F0h CM_PER_TIMER6_CLKCTRL Section 8.1.12.1.46
F4h CM_PER_MMC1_CLKCTRL Section 8.1.12.1.47
F8h CM_PER_MMC2_CLKCTRL Section 8.1.12.1.48
FCh CM_PER_TPTC1_CLKCTRL Section 8.1.12.1.49
100h CM_PER_TPTC2_CLKCTRL Section 8.1.12.1.50
10Ch CM_PER_SPINLOCK_CLKCTRL Section 8.1.12.1.51
110h CM_PER_MAILBOX0_CLKCTRL Section 8.1.12.1.52
11Ch CM_PER_L4HS_CLKSTCTRL Section 8.1.12.1.53
120h CM_PER_L4HS_CLKCTRL Section 8.1.12.1.54
12Ch CM_PER_OCPWP_L3_CLKSTCT Section 8.1.12.1.55
RL
130h CM_PER_OCPWP_CLKCTRL Section 8.1.12.1.56
140h CM_PER_PRU_ICSS_CLKSTCTR Section 8.1.12.1.57
L
144h CM_PER_CPSW_CLKSTCTRL Section 8.1.12.1.58
148h CM_PER_LCDC_CLKSTCTRL Section 8.1.12.1.59
14Ch CM_PER_CLKDIV32K_CLKCTRL Section 8.1.12.1.60
150h CM_PER_CLK_24MHZ_CLKSTCT Section 8.1.12.1.61
RL
549
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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