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Power, Reset, and Clock Management
Table 8-23. Bus Interface Clocks
SGX530 (MEMCLK & SYSCLK), LCDC, MPU Subsystem,
L3F_CLK GEMAC Switch (Ethernet), DAP, PRU-ICSS, EMIF, TPTC,
TPCC, OCMC RAM, DEBUGSS
L3S_CLK USB, TSC, GPMC, MMCHS2, McASP0, McASP1
DCAN0, DCAN1
DMTIMER2, DMTIMER3, DMTIMER4, DMTIMER5, DMTIMER6,
DMTIMER7
eCAP/eQEP/ePWM0, eCAP/eQEP/ePWM1,
eCAP/eQEP/ePWM2, eFuse
ELM, GPIO1, GPIO2, GPIO3
L4_PER_CLK
I2C1, I2C2, IEEE1500, LCD, Mailbox0
McASP0, McASP1
MMCHS0, MMCHS1, OCP Watchpoint,
SPI0, SPI1, Spinlock
UART1, UART2, UART3, UART4, UART5
ADC_TSC, Clock Manager, Control Module
DMTIMER0, DMTIMER1_1MS, GPIO0
L4_WKUP_CLK
I2C0, M3UMEM, M3DMEM, SmartReflex0, SmartReflex1
UART0, WDT1
8.1.6.7.1 Core PLL Configuration
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_CORE.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_CORE.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_CORE.DPLL_MULT and
DPLL_DIV to the desired values.
4. Configure M4, M5 and M6 dividers by setting HSDIVIDER_CLKOUT1_DIV bits in
CM_DIV_M4_DPLL_CORE,CM_DIV_M5_DPLL_CORE, and CM_DIV_M6_DPLL_CORE to the
desired values.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_CORE.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_CORE.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
Note: M4, M5, and M6 dividers can also be changed on-the-fly so that there is no need to put the PLL in
bypass and back to lock mode. After changing CM_DIV_Mx_DPLL_CORE.DPLL_CLKOUT_DIV, check
CM_DIV_Mx_DPLL_CORE.DPLL_HSDIVIDER_CLKOUT1_DIVCHACK for a toggle (a change from 0 to 1
or 1 to 0) to see if the change was acknowledged by the PLL.
8.1.6.8 Peripheral PLL Description
The Per PLL provides the source for peripheral functional clocks. The Per PLL comprises an ADPLLLJ
and additional dividers and muxes located in the PRCM as shown
527
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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