PRCM
Per PLL
(ADPLLLJ)
CLKDCOLDO
CLKINP
CLKOUT
PER_CLKOUTM2
(192 MHz)
USB_PHY_CLK (960 MHz)
To USB PHY
0
1
*Reset default zero
2
0
1
CLKINPULOW
ULOWCLKEN
ULOWPRIORITY
Controls
Master
Osc
(CLK_M_OSC)
ALT_CLK1
ALT_CLK2
TEST.CDR (via P1500)
Reset default = 0
PRU_ICSS_UART_CLK
MMC_CLK
SPI_CLK
UART_CLK
I2C_CLK
CONTROL_CLK32K
DIVRATIO_CTRL[0]*
/2
/4
/2
(96 MHz)
(48 MHz)
CLK_48
CLK_24
(32,768 Hz)
/732.4219
/366.2109
CLK_32KHZ
To DDR, Disp, MPU PLLs bypass
clocking PRCM SGX clock mux
Power, Reset, and Clock Management
www.ti.com
Figure 8-11. Peripheral PLL Structure
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode.
The PLL is locked at 960 MHz. The PLL output is divided by the M2 divider to generate a 192-MHz
CLKOUT. This clock is gated in the PRCM to form the PRU-ICSS UART clock. There is a /2 divider to
create 96 MHz for MMC_CLK. The clock is also divided within the PRCM by a fixed /4 divider to create a
48-MHz clock for the SPI, UART and I2C modules. The 48-MHz clock is further divided by a fixed /2
divider and a fixed /732.4219 divider to create an accurate 32.768-KHz clock for Timer and debounce use.
Table 8-24. Per PLL Typical Frequencies (MHz)
Power-On-Reset / PLL
OPP100 OPP50
(1) (2)
Bypass
Clock Source
Freq Freq
DIV Value Freq DIV Value DIV Value
(MHz) (MHz)
PLL Lock frequency PLL - - - 960 - 960
USB_PHY_CLK CLKDCOLDO - Held Low - 960 - 960
CLKOUT of
ADPLLLJ
CLKOUT uses PLL’s
N2 is 0 on Mstr Xtal/
PER_CLKOUTM2 M2 Divider when PLL 5 192 10 96
power-on-reset (N2+1)
is locked and PLL’s
N2 divider when PLL
Bypass
Mstr Xtal/
MMC_CLK PER_CLKOUTM2 2 2 96 2 48
((N2+1)*2)
SPI_CLK,
Mstr Xtal/
UART_CLK, PER_CLKOUTM2 4 4 48 4 24
((N2+1)*4)
I2C_CLK
CLK_24 CLK_48 2 CLK_48 /2 2 24 2 12
CLK_24 CLK_24 /
CLK_32KHZ 732.4219 732.4219 0.032768 366.2109 0.032768
(output of CLK_48/2) <CLK32_DIV>
(1)
For limitations using OPP50, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
(2)
Not all interfaces and peripheral modules are available in OPP50. For more information, see AM335x ARM Cortex-A8
Microprocessors (MPUs) Silicon Errata (literature number SPRZ360).
528
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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Copyright © 2011–2013, Texas Instruments Incorporated
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