Power, Reset, and Clock Management
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8.1.13.1.1 REVISION_PRM Register (offset = 0h) [reset = 0h]
REVISION_PRM is shown in Figure 8-164 and described in Table 8-179.
This register contains the IP revision code for the PRCM
Figure 8-164. REVISION_PRM Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Rev
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-179. REVISION_PRM Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
Reads returns 0.
7-0 Rev R 0h IP revision [
7:4] Major revision [
3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1
706
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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