FIFO management
FIFO transmit
FIFO receive
FIFO transmit interrupt
generation
FIFO transmit
DMA request generation
FIFO receive interrupt
generation
FIFO receive
DMA request generation
THR
64-byte transmit FIFO
RHR
64-byte receive FIFO
FCR
SCR
TLR
SSR[0]
Name
Register name
REG
Control
Status
SFLSR
SFREGL
SFREGH
uart-023
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Functional Description
19.3.6 FIFO Management
The FIFO is accessed by reading and writing the UARTi.UART_RHR and UARTi.UART_THR registers.
Parameters are controlled using the FIFO control register (UARTi.UART_FCR) and supplementary control
register (UARTi.UART_SCR). Reading the UARTi.UART_SSR[0] TX_FIFO_FULL bit at 1 means the FIFO
is full.
The UARTi.UART_TLR register controls the FIFO trigger level, which enables DMA and interrupt
generation. After reset, transmit (TX) and receive (RX) FIFOs are disabled; thus, the trigger level is the
default value of 1 byte. Figure 19-4 shows the FIFO management registers.
NOTE: Data in the UARTi.UART_RHR register is not overwritten when an overflow occurs.
NOTE: The UARTi.UART_SFLSR, UARTi.UART_SFREGL, and UARTi.UART_SFREGH status
registers are used in IrDA mode only. For use, see Section 19.3.8.2.6, IrDA Data Formatting.
Figure 19-4. FIFO Management Registers
3459
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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