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LCD Registers
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h]
LCDDMA_FB0_CEILING is shown in Figure 13-36 and described in Table 13-31.
Figure 13-36. LCDDMA_FB0_CEILING Register
31 30 29 28 27 26 25 24
fb0_ceil
R/W-0h
23 22 21 20 19 18 17 16
fb0_ceil
R/W-0h
15 14 13 12 11 10 9 8
fb0_ceil
R/W-0h
7 6 5 4 3 2 1 0
fb0_ceil Reserved
R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 13-31. LCDDMA_FB0_CEILING Register Field Descriptions
Bit Field Type Reset Description
31-2 fb0_ceil R/W 0h
Frame Buffer 0 Ceiling Address pointer
1-0 Reserved R 0h
1149
SPRUH73H–October 2011–Revised April 2013 LCD Controller
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