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20.1.5.17 TCAR2 Register (offset = 58h) [reset = 0h]
TCAR2 is shown in Figure 20-25 and described in Table 20-27.
When the appropriate (rising, falling or both) transition is detected in the edge detection logic and the
capture on second event is activated from the control register (TCLR), the current counter value is stored
to the TCAR2 register. Note that since the OCP clock is completely asynchronous with the timer clock,
some synchronization is done in order to make sure that the TCAR2 value is not read while it is being
updated due to some capture event. In 16-bit mode the following sequence must be followed to read the
TCAR2 register properly: First, perform an OCP Read Transaction to Read the lower 16-bits of the TCAR2
register. Second, perform an OCP Read Transaction to read the upper 16-bits of the TCAR2 register.
Figure 20-25. TCAR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPTURED_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-27. TCAR2 Register Field Descriptions
Bit Field Type Reset Description
31-0 CAPTURED_VALUE R/W 0h
Timer counter value captured on an external event trigger
3584
Timers SPRUH73H–October 2011–Revised April 2013
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