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UART Registers
19.5.1.53 TX_DMA_THRESHOLD Register
TX DMA threshold value
The TX_DMA_THRESHOLD register is shown in Figure 19-79 and described in Table 19-78.
Figure 19-86. TX_DMA_THRESHOLD Register
31 6 5 0
Reserved TX_DMA_THRESHOLD
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-85. TX_DMA_THRESHOLD Register Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reserved.
5-0 TX_DMA_THRES 0 Used to manually set the TX DMA threshold level. UART_MDR3[2] SET_TX_DMA_THRESHOLD
HOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will
be used without modifying the value of this register.
3549
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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