Multimedia Card Registers
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18.5.1.2 SD_SYSSTATUS Register (offset = 114h) [reset = 0h]
SD_SYSSTATUS is shown in Figure 18-38 and described in Table 18-21.
This register provides status information about the module excluding the interrupt status information.
Figure 18-38. SD_SYSSTATUS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved RESETDONE
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-21. SD_SYSSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 RESETDONE R 0h Internal Reset Monitoring.
Notethe debounce clock , the interface clock and the functional clock
shall be provided to the MMC/SD/SDIO host controller to allow the
internal reset monitoring.
0x0 = Internal module reset is on-going
0x1 = Reset completed
3392
Multimedia Card (MMC) SPRUH73H–October 2011–Revised April 2013
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