Ethernet Subsystem Registers
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14.5.5.25 RX0_CP Register (offset = A60h) [reset = 0h]
RX0_CP is shown in Figure 14-113 and described in Table 14-127.
CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER *
Figure 14-113. RX0_CP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_CP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-127. RX0_CP Register Field Descriptions
Bit Field Type Reset Description
31-0 RX_CP R/W 0h Rx Completion Pointer Register - This register is written by the host
with the buffer descriptor address for the last buffer processed by the
host during interrupt processing.
The port uses the value written to determine if the interrupt should
be deasserted.
Note: The value read is the completion pointer (interrupt
acknowledge) value that was written by the CPDMA DMA controller
(port).
The value written to this register by the host is compared with the
value that the port wrote to determine if the interrupt should remain
asserted.
The value written is not actually stored in the location.
The interrupt is deasserted if the two values are equal.
1348
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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