GPIO Registers
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25.4.1.22 GPIO_FALLINGDETECT Register (offset = 14Ch) [reset = 0h]
GPIO_FALLINGDETECT is shown in Figure 25-28 and described in Table 25-27.
The GPIO_FALLINGDETECT register is used to enable/disable for each input lines the falling-edge
(transition 1 to 0) detection to be used for the interrupt request generation.
Figure 25-28. GPIO_FALLINGDETECT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FALLINGDETECT[n]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-27. GPIO_FALLINGDETECT Register Field Descriptions
Bit Field Type Reset Description
31-0 FALLINGDETECT[n] R/W 0h
Falling Edge Interrupt Enable
0x0 = Disable IRQ on falling-edge detect.
0x1 = Enable IRQ on falling-edge detect.
4090
General-Purpose Input/Output SPRUH73H–October 2011–Revised April 2013
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