Functional Description
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24.3.1.3 Transfer Formats
This section describes the transfer formats supported by McSPI.
The flexibility of McSPI allows setting the parameters of the SPI transfer:
• SPI word length
• SPI enable generation programmable
• SPI enable assertion
• SPI enable polarity
• SPI clock frequency
• SPI clock phase
• SPI clock polarity
The consistency between SPI word length, clock phase and clock polarity of the master SPI device and
the communicating slave device remains under software responsibility.
24.3.1.3.1 Programmable Word Length
McSPI supports any SPI word from 4 to 32 bits long.
The SPI word length can be changed between transmissions to allow a master device to communicate
with peripheral slaves having different requirements.
24.3.1.3.2 Programmable SPI Enable Generation
McSPI is able to generate or not the SPI enable, if management of chip select is de-asserted a point to
point connection is mandatory. Only a single master of slave device can be connected to the SPI bus.
24.3.1.3.3 Programmable SPI Enable (SPIEN)
The polarity of the SPIEN signals is programmable. SPIEN signals can be active high or low.
The assertion of the SPIEN signals is programmable: SPIEN signals can be manually asserted or can be
automatically asserted.
Two consecutive words for two different slave devices may go along with active SPIEN signals with
different polarity.
24.3.1.3.4 Programmable SPI Clock (SPICLK)
The phase and the polarity of the SPI serial clock are programmable when McSPI is a SPI master device
or a SPI slave device. The baud rate of the SPI serial clock is programmable when McSPI is a SPI
master.
When McSPI is operating as a slave, the serial clock SPICLK is an input from the master.
24.3.1.3.5 Bit Rate
In Master Mode, an internal reference clock CLKSPIREF is used as an input of a programmable divider to
generate bit rate of the serial clock SPICLK. Granularity of this clock divider can be changed.
4000
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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