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UART Registers
19.5.1.47 Received FIFO Level (RXFIFO_LVL) Register
The Received FIFO Level register (RXFIFO_LVL) is shown in Figure 19-80 and described in Table 19-79.
Figure 19-80. RXFIFO_LVL Register
31 8 7 0
Reserved RXFIFO_LVL
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-79. RXFIFO_LVL Register Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved.
7-0 RXFIFO_LVL 0 Level of the RX FIFO
3543
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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