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Ethernet Subsystem Registers
14.5.7.10 RX_PRI_MAP Register (offset = 24h) [reset = 76543210h]
RX_PRI_MAP is shown in Figure 14-182 and described in Table 14-198.
CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER
Figure 14-182. RX_PRI_MAP Register
31 30 29 28 27 26 25 24
Reserved PRI7 Reserved PRI6
R-0h R/W-7h R-Eh R/W-76h
23 22 21 20 19 18 17 16
Reserved PRI5 Reserved PRI4
R-ECh R/W-765h R-ECAh R/W-7654h
15 14 13 12 11 10 9 8
Reserved PRI3 Reserved PRI2
R-ECA8h R/W-76543h R-ECA86h R/W-765432h
7 6 5 4 3 2 1 0
Reserved PRI1 Reserved PRI0
R-ECA864h R/W-7654321h R-ECA8642h R/W-76543210h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-198. RX_PRI_MAP Register Field Descriptions
Bit Field Type Reset Description
31 Reserved R 0h
30-28 PRI7 R/W 7h Priority
7 - A packet priority of 0x7 is mapped (changed) to this value.
27 Reserved R Eh
26-24 PRI6 R/W 76h Priority
6 - A packet priority of 0x6 is mapped (changed) to this value.
23 Reserved R ECh
22-20 PRI5 R/W 765h Priority
5 - A packet priority of 0x5 is mapped (changed) to this value.
19 Reserved R ECAh
18-16 PRI4 R/W 7654h Priority
4 - A packet priority of 0x4 is mapped (changed) to this value.
15 Reserved R ECA8h
14-12 PRI3 R/W 76543h Priority
3 - A packet priority of 0x3 is mapped (changed) to this value.
11 Reserved R ECA86h
10-8 PRI2 R/W 765432h Priority
2 - A packet priority of 0x2 is mapped (changed) to this value.
7 Reserved R ECA864h
6-4 PRI1 R/W 7654321h Priority
1 - A packet priority of 0x1 is mapped (changed) to this value.
3 Reserved R ECA8642h
2-0 PRI0 R/W 76543210h Priority
0 - A packet priority of 0x0 is mapped (changed) to this value.
1423
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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