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Ethernet Subsystem Registers
14.5.2.14 TX_PRI2_RATE Register (offset = 38h) [reset = 0h]
TX_PRI2_RATE is shown in Figure 14-42 and described in Table 14-53.
CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 2 RATE
Figure 14-42. TX_PRI2_RATE Register
31 30 29 28 27 26 25 24
Reserved PRIN_IDLE_CNT
R-0h R/W-0h
23 22 21 20 19 18 17 16
PRIN_IDLE_CNT
R/W-0h
15 14 13 12 11 10 9 8
Reserved PRIN_SEND_CNT
R-0h R/W-0h
7 6 5 4 3 2 1 0
PRIN_SEND_CNT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-53. TX_PRI2_RATE Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29-16 PRIN_IDLE_CNT R/W 0h Priority (
7:0) idle count
15-14 Reserved R 0h
13-0 PRIN_SEND_CNT R/W 0h Priority (
7:0) send count
1273
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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