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I2C Registers
21.4.1.23 I2C_SCLL Register (offset = B4h) [reset = 0h]
I2C_SCLL is shown in Figure 21-38 and described in Table 21-31.
CAUTION: During an active mode (I2C_EN bit in I2C_CON register is set to 1), no modification must be
done in this register. Changing it may result in an unpredictable behavior. This register is used to
determine the SCL low time value when master.
Figure 21-38. I2C_SCLL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
SCLL
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-31. I2C_SCLL Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 SCLL R/W 0h Fast/Standard mode SCL low time.
I2C master mode only, (FS).
This
8-bit value is used to generate the SCL low time value (tLOW) when
the peripheral is operated in master mode.
tLOW = (SCLL + 7) * ICLK time period, Value after reset is low (all 8
bits).
3755
SPRUH73H–October 2011–Revised April 2013 I2C
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