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DMTimer 1ms
20.2.5.5 TIER Register (offset = 1Ch) [reset = 0h]
TIER is shown in Figure 20-39 and described in Table 20-40.
This register controls (enable/disable) the interrupt events
Figure 20-39. TIER Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_IT_ENA OVF_IT_ENA MAT_IT_ENA
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-40. TIER Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
Reads return 0
2 TCAR_IT_ENA R/W 0h
Enable capture interrupt
0 = Dsb_capt : Disable capture interrupt
1 = Enb_capt : Enable capture interrupt
1 OVF_IT_ENA R/W 0h
Enable overflow interrupt
0 = Dsb_ovf : Disable overflow interrupt
1 = Enb_ovf : Enable overflow interrupt
0 MAT_IT_ENA R/W 0h
Enable match interrupt
0 = Dsb_match : Disable match interrupt
1 = Enb_match : Enable match interrupt
3603
SPRUH73H–October 2011–Revised April 2013 Timers
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