McSPI Registers
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24.4.1.14 McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX)
The McSPI DMA address aligned FIFO transmitter register (MCSPI_DAFTX) contains the SPI words to
transmit on the serial link when FIFO is used and the DMA address is aligned on 256 bit. This register is
an image of one of the MCSPI_TX(i) registers corresponding to the channel which have its FIFO enabled.
The MCSPI_DAFTX register is shown in Figure 24-39 and described in Table 24-25.
NOTE: See Chapter Access to data registers for the list of supported accesses.
The SPI words are transferred with MSB first.
Figure 24-39. McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX)
31 16
DAFTDATA
R/W-0
15 0
DAFTDATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 24-25. McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX) Field
Descriptions
Bit Field Value Description
31-0 DAFTDATA FIFO Data to transmit with DMA 256 bit aligned address.
This register is used only when MCSPI_MODULCTRL[FDAA] is set to ‘1’, and only one of the
MCSPI_CH(i)CONF[FFEW] of enabled channels is set. Without these conditions, any access to this
register will return a null value.
4054
Multichannel Serial Port Interface (McSPI) SPRUH73H–October 2011–Revised April 2013
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