Power, Reset, and Clock Management
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8.1.12.1.58 CM_PER_CPSW_CLKSTCTRL Register (offset = 144h) [reset = 2h]
CM_PER_CPSW_CLKSTCTRL is shown in Figure 8-80 and described in Table 8-87.
This register enables the clock domain state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 8-80. CM_PER_CPSW_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_CPSW Reserved CLKTRCTRL
_125MHz_GCLK
R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-87. CM_PER_CPSW_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-5 Reserved R 0h
4 CLKACTIVITY_CPSW_12 R 0h
This field indicates the state of the CPSW 125 MHz OCP clock in the
5MHz_GCLK
domain.
0x0 = Inact
0x1 = Act
3-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h
Controls the clock state transition of the CPSW OCP clock domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
Wakeup transition may however occur.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
transition on the domain.
0x3 = Reserved : Reserved.
608
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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