LCD Registers
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13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h]
CLKC_RESET is shown in Figure 13-45 and described in Table 13-40.
Figure 13-45. CLKC_RESET Register
31 30 29 28 27 26 25 24
Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved
R/W-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved main_rst dma_rst lidd_rst core_rst
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 13-40. CLKC_RESET Register Field Descriptions
Bit Field Type Reset Description
31-4 Reserved R/W 0h
3 main_rst R/W 0h Software Reset for the entire LCD module
1 = Reset Enable 0 = Reset Disable
2 dma_rst R/W 0h Software Reset for the DMA submodule
1 = Reset Enable 0 = Reset Disable
1 lidd_rst R/W 0h Software Reset for the LIDD submodule (character displays)
1 = Reset Enable 0 = Reset Disable
0 core_rst R/W 0h Software Reset for the Core, which encompasses the Raster Active
Matrix and Passive Matrix logic
1 = Reset Enable 0 = Reset Disable
1162
LCD Controller SPRUH73H–October 2011–Revised April 2013
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