Power, Reset, and Clock Management
www.ti.com
8.1.13.4.3 RM_MPU_RSTST Register (offset = 8h) [reset = 0h]
RM_MPU_RSTST is shown in Figure 8-178 and described in Table 8-196.
This register logs the different reset sources of the ALWON domain. Each bit is set upon release of the
domain reset signal. Must be cleared by software. [warm reset insensitive]
Figure 8-178. RM_MPU_RSTST Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved ICECRUSHER_MPU_ EMULATION_MPU_R Reserved Reserved Reserved Reserved
RST ST
R-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-196. RM_MPU_RSTST Register Field Descriptions
Bit Field Type Reset Description
31-15 Reserved R 0h
14-8 Reserved R 0h
7 Reserved R 0h
6 ICECRUSHER_MPU_RS R/W 0h
MPU Processor has been reset due to MPU ICECRUSHER1 reset
T
event
0x0 = RESET_NO : No icecrusher reset
0x1 = RESET_YES : MPU Processor has been reset upon
icecursher reset
5 EMULATION_MPU_RST R/W 0h MPU Processor has been reset due to emulation reset source e.g.
assert reset command initiated by the icepick module
0x0 = RESET_NO : No emulation reset
0x1 = RESET_YES : MPU Processor has been reset upon emulation
reset
4 Reserved R 0h
3 Reserved R 0h
2 Reserved R 0h
1-0 Reserved R 0h
8.1.13.5 PRM_DEVICE Registers
Table 8-197 lists the memory-mapped registers for the PRM_DEVICE. All register offset addresses not
listed in Table 8-197 should be considered as reserved locations and the register contents should not be
modified.
Table 8-197. PRM_DEVICE REGISTERS
Offset Acronym Register Name Section
0h PRM_RSTCTRL Section 8.1.13.5.1
4h PRM_RSTTIME Section 8.1.13.5.2
8h PRM_RSTST Section 8.1.13.5.3
724
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
