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Enhanced Capture (eCAP) Module
15.3.4.1.7 ECCTL1 Register (offset = 28h) [reset = 0h]
ECCTL1 is shown in Figure 15-122 and described in Table 15-115.
Figure 15-122. ECCTL1 Register
15 14 13 12 11 10 9 8
FREE_SOFT PRESCALE CAPLDEN
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-115. ECCTL1 Register Field Descriptions
Bit Field Type Reset Description
15-14 FREE_SOFT R/W 0h
Emulation Control
0x0 = TSCTR counter stops immediately on emulation suspend.
0x1 = TSCTR counter runs until = 0.
0x2 = TSCTR counter is unaffected by emulation suspend (Run
Free).
0x3 = TSCTR counter is unaffected by emulation suspend (Run
Free).
13-9 PRESCALE R/W 0h
Event Filter prescale select ...
0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler)
0x1 = Divide by 2
0x2 = Divide by 4
0x3 = Divide by 6
0x4 = Divide by 8
0x5 = Divide by 10
0x1E = Divide by 60
0x1F = Divide by 62
8 CAPLDEN R/W 0h Enable Loading of CAP
1-4 registers on a capture event
0x0 = Disable CAP1-4 register loads at capture event time.
0x1 = Enable CAP1-4 register loads at capture event time.
7 CTRRST4 R/W 0h
Counter Reset on Capture Event 4
0x0 = Do not reset counter on Capture Event 4 (absolute time stamp
operation)
0x1 = Reset counter after Capture Event 4 time-stamp has been
captured (used in difference mode operation)
6 CAP4POL R/W 0h
Capture Event 4 Polarity select
0x0 = Capture Event 4 triggered on a rising edge (RE)
0x1 = Capture Event 4 triggered on a falling edge (FE)
5 CTRRST3 R/W 0h
Counter Reset on Capture Event 3
0x0 = Do not reset counter on Capture Event 3 (absolute time
stamp)
0x1 = Reset counter after Event 3 time-stamp has been captured
(used in difference mode operation)
4 CAP3POL R/W 0h
Capture Event 3 Polarity select
0x0 = Capture Event 3 triggered on a rising edge (RE)
0x1 = Capture Event 3 triggered on a falling edge (FE)
1641
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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