www.ti.com
Ethernet Subsystem Registers
14.5.6.1 P0_CONTROL Register (offset = 0h) [reset = 0h]
P0_CONTROL is shown in Figure 14-121 and described in Table 14-136.
CPSW PORT 0 CONTROL REGISTER
Figure 14-121. P0_CONTROL Register
31 30 29 28 27 26 25 24
Reserved P0_DLR_CPDMA_CH Reserved P0_PASS_PRI_TAGG
ED
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved P0_VLAN_LTYPE2_E P0_VLAN_LTYPE1_E Reserved P0_DSCP_PRI_EN
N N
R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-136. P0_CONTROL Register Field Descriptions
Bit Field Type Reset Description
30-28 P0_DLR_CPDMA_CH R/W 0h Port 0 DLR CPDMA Channel This field indicates the CPDMA
channel that DLR packets will be received on.
24 P0_PASS_PRI_TAGGED R/W 0h Port 0 Pass Priority Tagged
0 - Priority tagged packets have the zero VID replaced with the input
port P0_PORT_VLAN
[11:0]
1 - Priority tagged packets are processed unchanged.
21 P0_VLAN_LTYPE2_EN R/W 0h Port 0 VLAN LTYPE 2 enable
0 - disabled
1 - enabled
20 P0_VLAN_LTYPE1_EN R/W 0h Port 0 VLAN LTYPE 1 enable
0 - disabled
1 - enabled
16 P0_DSCP_PRI_EN R/W 0h Port 0 DSCP Priority Enable
0 - DSCP priority disabled
1 - DSCP priority enabled.
All non-tagged IPV4 packets have their received packet priority
determined by mapping the 6 TOS bits through the port DSCP
priority mapping registers.
1357
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
