TINT12
TINT34
L4 Peripheral
Interconnect
MPU Subsystem
and PRU-ICSS
Interrupts
McASP
Subsystem
x_intr_pend
MCAx_AHCLKX
AHCLKX
ACLKX
MCAx_ACLKX
MCAx_AFSX
AFSX
AHCLKR
EDMA
xevent_dreq
revent_dreq
aux_clk
McASPx Pads
MCAx_AHCLKR
MCAx_ACLKR
MCAx_AFSR
MCAx_AXR0
MCAx_AXR1
MCAx_AXR2
MCAx_AXR3
ACLKR
AFSR
AMUTE
AMUTEIN
AXR0
AXR1
AXR2
AXR3
AXR[9:4]
AXEVT0
AREVT0
r_intr_pend
L3 Slow
Interconnect
CFG Interface
DMA/Data
Interface
PRCM
CLK_M_OSC
MCASP_FCLK
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Integration
22.2 Integration
The device contains two instantiations of the McASP subsystem: McASP0 and McASP1. The McASP
subsystem includes a McASP peripheral, and transmit/receive buffers.
Each McASP is configured with four serializers.
Figure 22-1. McASP0–1 Integration
22.2.1 McASP Connectivity Attributes
The general connectivity attributes for the McASP modules are summarized in Table 22-1
Table 22-1. McASP Connectivity Attributes
Attributes Type
Power Domain Peripheral Domain
Clock Domain PD_PER_L3S_GCLK (OCP Clock)
PD_PER_MCASP_FCLK (Aux Clock)
Reset Signals PER_DOM_RST_N
Idle/Wakeup Signals Smart Idle
Interrupt Requests
1 Transmit Interrupt per instance
x_intr_pend - to MPU Subsystem (MCATXINTx) and PRU-
ICSS (mcasp_x_intr_pend)
1 Receive Interrupt
r_intr_pend - to MPU Subsystem (MCARXINTx) and PRU-
ICSS (mcasp_r_intr_pend)
DMA Requests 2 DMA requests per instance to EDMA (Transmit: AXEVTx,
Receive: AREVTx)
Physical Address L3 Slow slave port (data)
L4 Peripheral slave port (CFG)
3771
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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