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Touchscreen Controller Registers
12.5.1.13 ADC_CLKDIV Register (offset = 4Ch) [reset = 0h]
ADC_CLKDIV is shown in Figure 12-17 and described in Table 12-17.
ADC clock divider register@TSC_ADC_SS_Clock_Divider Register
Figure 12-17. ADC_CLKDIV Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
ADC_ClkDiv
R/W-0h
7 6 5 4 3 2 1 0
ADC_ClkDiv
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-17. ADC_CLKDIV Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-0 ADC_ClkDiv R/W 0h The input ADC clock will be divided by this value and sent to the
AFE.
Program to the value minus 1
1051
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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