CONTROL_MODULE Registers
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9.3.8 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h]
clk32kdivratio_ctrl is shown in Figure 9-11 and described in Table 9-18.
Figure 9-11. clk32kdivratio_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved clkdivopp50_en
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-18. clk32kdivratio_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 clkdivopp50_en R/W 0h 0 : OPP100 operation, use ratio for 24MHz to 32KHz division
1 : OPP50 operation, use ratio for 12MHz to 32KHz division
770
Control Module SPRUH73H–October 2011–Revised April 2013
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