UART Registers
www.ti.com
19.5.1.18 Trigger Level Register (TLR)
This register stores the programmable transmit and receive FIFO trigger levels used for DMA and IRQ
generation. The trigger level register (TLR) is shown in Figure 19-51 and described in Table 19-47.
Figure 19-51. Trigger Level Register (TLR)
15 8 7 4 3 0
Reserved RX_FIFO_TRIG_ DMA TX_FIFO_TRIG_ DMA
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-47. Trigger Level Register (TLR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-4 RX_FIFO_TRIG_ DMA 0-Fh Receive FIFO trigger level. See Table 19-48.
3-0 TX_FIFO_TRIG_ DMA 0-Fh Transmit FIFO trigger level. See Table 19-49.
Table 19-48. RX FIFO Trigger Level Setting Summary
SCR[7] TLR[7:4] Description
0 0 Defined by FCR[7:6] (either 8, 16, 56, 60 characters).
0 ≠ 0000 Defined by TLR[7:4] (from 4 to 60 characters with a granularity of 4 characters).
1 any value Defined by the concatenated value of TLR[7:4] and FCR[7:6] (from 1 to 63 characters with a
granularity of 1 character). Note: the combination of TLR[7:4] = 0000 and FCR[7:6] = 00 (all zeros)
is not supported (minimum of 1 character is required). All zeros results in unpredictable behavior.
Table 19-49. TX FIFO Trigger Space Setting Summary
SCR[6] TLR[3:0] Description
0 0 Defined by FCR[5:4] (either 8, 16, 32, 56 spaces).
0 ≠ 0000 Defined by TLR[3:0] (from 4 to 60 spaces with a granularity of 4 spaces).
1 any value Defined by the concatenated value of TLR[3:0] and FCR[5:4] (from 1 to 63 spaces with a granularity
of 1 space). Note: the combination of TLR[3:0] = 0000 and FCR[5:4] = 00 (all zeros) is not
supported (minimum of 1 space is required). All zeros results in unpredictable behavior.
3522
Universal Asynchronous Receiver/Transmitter (UART) SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
