I2C Registers
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21.4.1.11 I2C_DMARXENABLE_CLR Register (offset = 40h) [reset = 0h]
I2C_DMARXENABLE_CLR is shown in Figure 21-26 and described in Table 21-19.
The 1-bit field disables a receive DMA request. Writing a 1 to a bit will clear it to 0. Another result of
setting to 1 the DMARX_ENABLE_CLEAR field, is the reset of the DMA RX request and wakeup lines.
Writing a 0 will have no effect, that is, the register value is not modified.
Figure 21-26. I2C_DMARXENABLE_CLR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved DMARX_ENABLE_CL
EAR
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-19. I2C_DMARXENABLE_CLR Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 DMARX_ENABLE_CLEA R/W 0h
Receive DMA channel enable clear.
R
3738
I2C SPRUH73H–October 2011–Revised April 2013
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