TINT 12
TINT 34
L4Peripheral
Interconnect
MPU Subsystem
Interrupts
LCD Controller
intr_pend
LCD_DATA[15:0]
lcd_pixel[15:0]
lcd_pixel[23:16]
LCD_DATA[23:16]
lcd_lp
lcd_clk
LCDC Pads
LCD_HSYNC
LCD_VSYNC
LCD_MEMORY_CLK
lcd_fp
lcd_mclk
L3Fast
Interconnect
CFG Interface
DMA Master
Interface
PRCM
Disp PLL
CLKOUT
LCD_CLK
LCD_PCLK
lcd_cp
lcd_int_clk
Integration
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13.2 Integration
The device includes an LCD Controller that reads display data from external memory and drives several
different types of LCD displays. The LCD Controller integration is shown in Figure 13-2.
Figure 13-2. LCD Controller Integration
13.2.1 LCD Controller Connectivity Attributes
The general connectivity attributes for the LCDC subsystems are shown in Table 13-1.
Table 13-1. LCD Controller Connectivity Attributes
Attributes Type
Power Domain Peripheral Domain
Clock Domain
PD_PER_LCD_L3_GCLK (OCP Master Clock)
PD_PER_LCD_L3_GCLK (OCP Slave Clock)
PD_PER_LCD_GCLK (Functional Clock)
Reset Signals PER_DOM_RST_N
Idle/Wakeup Signals Standby
Smart Idle
Interrupt Requests 1 Interrupt to MPU Subsystem (LCDCINT)
DMA Requests None
Physical Address L4 Peripheral Slave Port
1100
LCD Controller SPRUH73H–October 2011–Revised April 2013
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