Ethernet Subsystem Registers
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14.5.6.8 P0_CPDMA_RX_CH_MAP Register (offset = 20h) [reset = 0h]
P0_CPDMA_RX_CH_MAP is shown in Figure 14-128 and described in Table 14-143.
CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL
Figure 14-128. P0_CPDMA_RX_CH_MAP Register
31 30 29 28 27 26 25 24
Reserved P2_PRI3 Reserved P2_PRI2
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved P2_PRI1 Reserved P2_PRI0
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved P1_PRI3 Reserved P1_PRI2
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved P1_PRI1 Reserved P1_PRI0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-143. P0_CPDMA_RX_CH_MAP Register Field Descriptions
Bit Field Type Reset Description
30-28 P2_PRI3 R/W 0h
Port 2 Priority 3 packets go to this CPDMA Rx Channel
26-24 P2_PRI2 R/W 0h
Port 2 Priority 2 packets go to this CPDMA Rx Channel
22-20 P2_PRI1 R/W 0h
Port 2 Priority 1 packets go to this CPDMA Rx Channel
18-16 P2_PRI0 R/W 0h
Port 2 Priority 0 packets go to this CPDMA Rx Channel
14-12 P1_PRI3 R/W 0h
Port 1 Priority 3 packets go to this CPDMA Rx Channel
10-8 P1_PRI2 R/W 0h
Port 1 Priority 2 packets go to this CPDMA Rx Channel
6-4 P1_PRI1 R/W 0h
Port 1 Priority 1 packets go to this CPDMA Rx Channel
2-0 P1_PRI0 R/W 0h
Port 1 Priority 0 packets go to this CPDMA Rx Channel
1364
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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