Ethernet Subsystem Registers
www.ti.com
14.5.6.27 P1_RX_DSCP_PRI_MAP0 Register (offset = 130h) [reset = 0h]
P1_RX_DSCP_PRI_MAP0 is shown in Figure 14-147 and described in Table 14-162.
CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0
Figure 14-147. P1_RX_DSCP_PRI_MAP0 Register
31 30 29 28 27 26 25 24
Reserved PRI7 Reserved PRI6
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved PRI5 Reserved PRI4
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved PRI3 Reserved PRI2
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved PRI1 Reserved PRI0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-162. P1_RX_DSCP_PRI_MAP0 Register Field Descriptions
Bit Field Type Reset Description
30-28 PRI7 R/W 0h Priority
7 - A packet TOS of 0d7 is mapped to this received packet priority.
26-24 PRI6 R/W 0h Priority
6 - A packet TOS of 0d6 is mapped to this received packet priority.
22-20 PRI5 R/W 0h Priority
5 - A packet TOS of 0d5 is mapped to this received packet priority.
18-16 PRI4 R/W 0h Priority
4 - A packet TOS of 0d4 is mapped to this received packet priority.
14-12 PRI3 R/W 0h Priority
3 - A packet TOS of 0d3 is mapped to this received packet priority.
10-8 PRI2 R/W 0h Priority
2 - A packet TOS of 0d2 is mapped to this received packet priority.
6-4 PRI1 R/W 0h Priority
1 - A packet TOS of 0d1 is mapped to this received packet priority.
2-0 PRI0 R/W 0h Priority
0 - A packet TOS of 0d0 is mapped to this received packet priority.
1384
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
