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8.1.13.1.3 PRM_IRQENABLE_MPU Register (offset = 8h) [reset = 0h]
PRM_IRQENABLE_MPU is shown in Figure 8-166 and described in Table 8-181.
This register is used to enable and disable events used to trigger MPU interrupt activation.
Figure 8-166. PRM_IRQENABLE_MPU Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_disp_recal_en dpll_ddr_recal_en dpll_per_recal_en dpll_core_recal_en dpll_mpu_recal_en ForceWkup_en Reserved Transition_en
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-181. PRM_IRQENABLE_MPU Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15 dpll_disp_recal_en R/W 0h
Interrupt enable for disp dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
14 dpll_ddr_recal_en R/W 0h
Interrupt enable for ddr dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
13 dpll_per_recal_en R/W 0h
Interrupt enable for usb dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
12 dpll_core_recal_en R/W 0h
Interrupt enable for core dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
11 dpll_mpu_recal_en R/W 0h
Interrupt enable for mpu dpll recaliberation
0 = DIS : Disables dpll recaliberation
1 = EN : ENAbles dpll recaliberation
10 ForceWkup_en R/W 0h
Software supervised Froce Wakeup completed event interrupt
enable
0 = irq_msk : Interrupt is masked
1 = irq_en : Interrupt is enabled
9 Reserved R 0h
8 Transition_en R/W 0h
Software supervised transition completed event interrupt enable (any
domain)
0 = irq_msk : Interrupt is masked
1 = irq_en : Interrupt is enabled
7-6 Reserved R 0h
5-1 Reserved R 0h
0 Reserved R 0h
708
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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