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DMTimer 1ms
20.2.5.13 TCAR1 Register (offset = 3Ch) [reset = 0h]
TCAR1 is shown in Figure 20-47 and described in Table 20-48.
This register holds the value of the first counter register capture
Figure 20-47. TCAR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPTURE_VALUE1
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-48. TCAR1 Register Field Descriptions
Bit Field Type Reset Description
31-0 CAPTURE_VALUE1 R 0h
The value of first captured counter register
3613
SPRUH73H–October 2011–Revised April 2013 Timers
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