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USB Registers
16.5.1.24 IRQDMAENABLE1 Register (offset = 144h) [reset = 0h]
IRQDMAENABLE1 is shown in Figure 16-45 and described in Table 16-53.
Figure 16-45. IRQDMAENABLE1 Register
31 30 29 28 27 26 25 24
DMA_EN_RX1_15 Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved DMA_EN_RX1_1 Reserved
R/W-0h
15 14 13 12 11 10 9 8
DMA_EN_TX1_15 Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved DMA_EN_TX1_1 Reserved
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-53. IRQDMAENABLE1 Register Field Descriptions
Bit Field Type Reset Description
31 DMA_EN_RX1_15 R/W 0h DMA threshold enable value for rx_pkt_cmp_1 for USB1 Endpoint
15.
...
...
...
...
...
17 DMA_EN_RX1_1 R/W 0h DMA threshold enable value for rx_pkt_cmp_1 for USB1 Endpoint 1.
15 DMA_EN_TX1_15 R/W 0h DMA threshold enable value for tx_pkt_cmp_1 for USB1 Endpoint
15.
...
...
...
...
...
1 DMA_EN_TX1_1 R/W 0h DMA threshold enable value for tx_pkt_cmp_1 for USB1 Endpoint 1.
1785
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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