USB Registers
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16.5.6.1 DMA_SCHED_CTRL Register (offset = 0h) [reset = 0h]
DMA_SCHED_CTRL is shown in Figure 16-275 and described in Table 16-288.
Figure 16-275. DMA_SCHED_CTRL Register
31 30 29 28 27 26 25 24
ENABLE Reserved
R/W-0h
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
LAST_ENTRY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-288. DMA_SCHED_CTRL Register Field Descriptions
Bit Field Type Reset Description
31 ENABLE R/W 0h This is the enable bit for the scheduler and is encoded as follows:
0 = scheduler is disabled and will no longer fetch entries from the
scheduler table or pass credits to the DMA controller
1 = scheduler is enabled This bit should only be set after the table
has been initialized.
7-0 LAST_ENTRY R/W 0h This field indicates the last valid entry in the scheduler table.
There are 64 words in the table and there are 4 entries in each word.
The table can be programmed with any integer number of entries
from 1 to 256.
The corresponding encoding for this field is as follows:
0 = 1 entry
1 = 2 entries ...
254 = 255 entries
255 = 256 entries CPPI DMA Scheduler Control Registers
2082
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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