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RTC_SS
20.3.5.27 RTC_IRQWAKEEN Register (offset = 7Ch) [reset = 0h]
RTC_IRQWAKEEN is shown in Figure 20-87 and described in Table 20-90.
Figure 20-87. RTC_IRQWAKEEN Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved ALARM_WAKEEN TIMER_WAKEEN
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-90. RTC_IRQWAKEEN Register Field Descriptions
Bit Field Type Reset Description
31-2 Reserved R 0h
1 ALARM_WAKEEN R/W 0h
Wakeup generation for event Alarm.
0x0 = Wakeup disabled
0x1 = Wakeup enabled
0 TIMER_WAKEEN R/W 0h
Wakeup generation for event Timer.
0x0 = Wakeup disabled
0x1 = Wakeup enabled
3661
SPRUH73H–October 2011–Revised April 2013 Timers
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