Texas Instruments AM335 Series Technical Reference Manual

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Table 8-91. CM_WKUP REGISTERS (continued)
Offset Acronym Register Name Section
5Ch CM_IDLEST_DPLL_CORE This register allows monitoring the master clock activity. Section 8.1.12.2.24
This register is read only and automatically updated.
[warm reset insensitive]
60h CM_SSC_DELTAMSTEP_DPLL_C Control the DeltaMStep parameter for Spread Spectrum Section 8.1.12.2.25
ORE Clocking technique DeltaMStep is split into fractional
and integer part.
[warm reset insensitive]
64h CM_SSC_MODFREQDIV_DPLL_C Control the Modulation Frequency (Fm) for Spread Section 8.1.12.2.26
ORE Spectrum Clocking technique by defining it as a ratio of
DPLL_REFCLK/4 Fm =
[DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA *
2^MODFREQDIV_EXPONENT [warm reset insensitive]
68h CM_CLKSEL_DPLL_CORE This register provides controls over the DPLL. Section 8.1.12.2.27
6Ch CM_AUTOIDLE_DPLL_PER This register provides automatic control over the DPLL Section 8.1.12.2.28
activity.
70h CM_IDLEST_DPLL_PER This register allows monitoring the master clock activity. Section 8.1.12.2.29
This register is read only and automatically updated.
[warm reset insensitive]
74h CM_SSC_DELTAMSTEP_DPLL_P Control the DeltaMStep parameter for Spread Spectrum Section 8.1.12.2.30
ER Clocking technique DeltaMStep is split into fractional
and integer part.
[warm reset insensitive]
78h CM_SSC_MODFREQDIV_DPLL_P Control the Modulation Frequency (Fm) for Spread Section 8.1.12.2.31
ER Spectrum Clocking technique by defining it as a ratio of
DPLL_REFCLK/4 Fm =
[DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA *
2^MODFREQDIV_EXPONENT [warm reset insensitive]
7Ch CM_CLKDCOLDO_DPLL_PER This register provides controls over the digitally Section 8.1.12.2.32
controlled oscillator output of the PER DPLL.
80h CM_DIV_M4_DPLL_CORE This register provides controls over the CLKOUT1 o/p of Section 8.1.12.2.33
the HSDIVIDER.
84h CM_DIV_M5_DPLL_CORE This register provides controls over the CLKOUT2 o/p of Section 8.1.12.2.34
the HSDIVIDER.
88h CM_CLKMODE_DPLL_MPU This register allows controlling the DPLL modes. Section 8.1.12.2.35
8Ch CM_CLKMODE_DPLL_PER This register allows controlling the DPLL modes. Section 8.1.12.2.36
90h CM_CLKMODE_DPLL_CORE This register allows controlling the DPLL modes. Section 8.1.12.2.37
94h CM_CLKMODE_DPLL_DDR This register allows controlling the DPLL modes. Section 8.1.12.2.38
98h CM_CLKMODE_DPLL_DISP This register allows controlling the DPLL modes. Section 8.1.12.2.39
9Ch CM_CLKSEL_DPLL_PERIPH This register provides controls over the DPLL. Section 8.1.12.2.40
A0h CM_DIV_M2_DPLL_DDR This register provides controls over the M2 divider of the Section 8.1.12.2.41
DPLL.
A4h CM_DIV_M2_DPLL_DISP This register provides controls over the M2 divider of the Section 8.1.12.2.42
DPLL.
A8h CM_DIV_M2_DPLL_MPU This register provides controls over the M2 divider of the Section 8.1.12.2.43
DPLL.
ACh CM_DIV_M2_DPLL_PER This register provides controls over the M2 divider of the Section 8.1.12.2.44
DPLL.
B0h CM_WKUP_WKUP_M3_CLKCTRL This register manages the WKUP M3 clocks. Section 8.1.12.2.45
B4h CM_WKUP_UART0_CLKCTRL This register manages the UART0 clocks. Section 8.1.12.2.46
B8h CM_WKUP_I2C0_CLKCTRL This register manages the I2C0 clocks. Section 8.1.12.2.47
BCh CM_WKUP_ADC_TSC_CLKCTRL This register manages the ADC clocks. Section 8.1.12.2.48
C0h CM_WKUP_SMARTREFLEX0_CL This register manages the SmartReflex0 clocks. Section 8.1.12.2.49
KCTRL
C4h CM_WKUP_TIMER1_CLKCTRL This register manages the TIMER1 clocks. Section 8.1.12.2.50
613
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English