Texas Instruments AM335 Series Technical Reference Manual

Power, Reset, and Clock Management www.ti.com
Table 8-91. CM_WKUP REGISTERS (continued)
Offset Acronym Register Name Section
Ch CM_WKUP_L4WKUP_CLKCTRL This register manages the L4WKUP clocks. Section 8.1.12.2.4
10h CM_WKUP_TIMER0_CLKCTRL This register manages the TIMER0 clocks. Section 8.1.12.2.5
14h CM_WKUP_DEBUGSS_CLKCTRL This register manages the DEBUGSS clocks. Section 8.1.12.2.6
18h CM_L3_AON_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.2.7
It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
1Ch CM_AUTOIDLE_DPLL_MPU This register provides automatic control over the DPLL Section 8.1.12.2.8
activity.
20h CM_IDLEST_DPLL_MPU This register allows monitoring the master clock activity. Section 8.1.12.2.9
This register is read only and automatically
updated.[warm reset insensitive]
24h CM_SSC_DELTAMSTEP_DPLL_M Control the DeltaMStep parameter for Spread Spectrum Section 8.1.12.2.10
PU Clocking technique DeltaMStep is split into fractional
and integer part.
[warm reset insensitive]
28h CM_SSC_MODFREQDIV_DPLL_ Control the Modulation Frequency (Fm) for Spread Section 8.1.12.2.11
MPU Spectrum Clocking technique by defining it as a ratio of
DPLL_REFCLK/4 Fm =
[DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA *
2^MODFREQDIV_EXPONENT [warm reset insensitive]
2Ch CM_CLKSEL_DPLL_MPU This register provides controls over the DPLL. Section 8.1.12.2.12
30h CM_AUTOIDLE_DPLL_DDR This register provides automatic control over the DPLL Section 8.1.12.2.13
activity.
34h CM_IDLEST_DPLL_DDR This register allows monitoring the master clock activity. Section 8.1.12.2.14
This register is read only and automatically updated.
[warm reset insensitive]
38h CM_SSC_DELTAMSTEP_DPLL_D Control the DeltaMStep parameter for Spread Spectrum Section 8.1.12.2.15
DR Clocking technique DeltaMStep is split into fractional
and integer part.
[warm reset insensitive]
3Ch CM_SSC_MODFREQDIV_DPLL_D Control the Modulation Frequency (Fm) for Spread Section 8.1.12.2.16
DR Spectrum Clocking technique by defining it as a ratio of
DPLL_REFCLK/4 Fm =
[DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA *
2^MODFREQDIV_EXPONENT [warm reset insensitive]
40h CM_CLKSEL_DPLL_DDR This register provides controls over the DPLL. Section 8.1.12.2.17
44h CM_AUTOIDLE_DPLL_DISP This register provides automatic control over the DPLL Section 8.1.12.2.18
activity.
48h CM_IDLEST_DPLL_DISP This register allows monitoring the master clock activity. Section 8.1.12.2.19
This register is read only and automatically updated.
[warm reset insensitive]
4Ch CM_SSC_DELTAMSTEP_DPLL_D Control the DeltaMStep parameter for Spread Spectrum Section 8.1.12.2.20
ISP Clocking technique DeltaMStep is split into fractional
and integer part.
[warm reset insensitive]
50h CM_SSC_MODFREQDIV_DPLL_D Control the Modulation Frequency (Fm) for Spread Section 8.1.12.2.21
ISP Spectrum Clocking technique by defining it as a ratio of
DPLL_REFCLK/4 Fm =
[DPLL_REFCLK/4]/MODFREQDIV MODFREQDIV =
MODFREQDIV_MANTISSA *
2^MODFREQDIV_EXPONENT [warm reset insensitive]
54h CM_CLKSEL_DPLL_DISP This register provides controls over the DPLL. Section 8.1.12.2.22
58h CM_AUTOIDLE_DPLL_CORE This register provides automatic control over the DPLL Section 8.1.12.2.23
activity.
612
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English