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Texas Instruments AM335 Series Technical Reference Manual
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UART
Registers
www.ti.com
3506
Universal
Asynchronous
Receiver/Transmitter
(UART)
SPRUH73H
–
October
2011
–
Revised
April
2013
Submit
Documentation
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Copyright
©
2011–2013,
Texas
Instruments
Incorporated
3505
3507
Table of Contents
Table of Contents
2
Preface
149
1 Introduction
150
1.1 AM335x Family
150
1.1.1 Device Features
150
1.1.2 Device Identification
151
1.1.3 Feature Identification
151
1.2 Silicon Revision Functional Differences and Enhancements
153
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes
153
1.2.2 Changed BOOTP Identifier
153
1.2.3 Changed Product String in USB Descriptor
153
1.2.4 Added DPLL Power Switch Control and Status Registers
153
1.2.5 Added Control for CORE SRAM LDO Retention Mode
153
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing
153
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)
153
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register
154
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay
154
1.2.10 Changed Default Value of RMII Clock Source
154
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot
154
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants
154
2 Memory Map
155
2.1 ARM Cortex-A8 Memory Map
155
3 ARM MPU Subsystem
164
3.1 ARM Cortex-A8 MPU Subsystem
165
3.1.1 Features
166
3.1.2 MPU Subsystem Integration
166
3.1.3 MPU Subsystem Clock and Reset Distribution
167
3.1.3.1 Clock Distribution
167
3.1.3.2 Reset Distribution
169
3.1.4 ARM Subchip
170
3.1.4.1 ARM Overview
170
3.1.4.2 ARM Description
170
3.1.4.2.1 ARM® Cortex™-A8 Instruction, Data, and Private Peripheral Port
170
3.1.4.2.2 Secure Monitor Calls to Access CP15 Registers
170
3.1.4.2.3 ARM Core Supported Features
171
3.1.5 Interrupt Controller
171
3.1.6 Power Management
171
3.1.6.1 Power Domains
171
3.1.6.2 Power States
173
3.1.6.3 Power Modes
173
3.1.7 ARM Programming Model
174
3.1.7.1 Clock Control
174
3.1.7.2 MPU Power Mode Transitions
174
3.1.7.2.1 Basic Power-On Reset
174
3.1.7.2.2 MPU Into Standby Mode
174
3.1.7.2.3 MPU Out Of Standby Mode
175
3.1.7.2.4 MPU Power On From a Powered-Off State
175
4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
176
4.1 Introduction
177
5 Graphics Accelerator (SGX)
178
5.1 Introduction
179
5.1.1 POWERVR SGX Main Features
179
5.1.2 SGX 3D Features
179
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features
180
5.1.4 Unsupported Features
181
5.2 Integration
182
5.2.1 SGX530 Connectivity Attributes
182
5.2.2 SGX530 Clock and Reset Management
182
5.2.3 SGX530 Pin List
183
5.3 Functional Description
184
5.3.1 SGX Block Diagram
184
5.3.2 SGX Elements Description
184
6 Interrupts
186
6.1 Functional Description
187
6.1.1 Interrupt Processing
188
6.1.1.1 Input Selection
188
6.1.1.2 Masking
188
6.1.1.2.1 Individual Masking
188
6.1.1.2.2 Priority Masking
188
6.1.1.3 Priority Sorting
188
6.1.2 Register Protection
189
6.1.3 Module Power Saving
189
6.1.4 Error Handling
189
6.1.5 Interrupt Handling
189
6.2 Basic Programming Model
190
6.2.1 Initialization Sequence
190
6.2.2 INTC Processing Sequence
190
6.2.3 INTC Preemptive Processing Sequence
194
6.2.4 Interrupt Preemption
198
6.2.5 ARM A8 INTC Spurious Interrupt Handling
198
6.3 ARM Cortex-A8 Interrupts
199
6.4 PWM Events
203
6.5 Interrupt Controller Registers
204
6.5.1 INTC Registers
204
6.5.1.1 INTC_REVISION Register (offset = 0h) [reset = 50h]
206
6.5.1.2 INTC_SYSCONFIG Register (offset = 10h) [reset = 0h]
207
6.5.1.3 INTC_SYSSTATUS Register (offset = 14h) [reset = 0h]
208
6.5.1.4 INTC_SIR_IRQ Register (offset = 40h) [reset = FFFFFF80h]
209
6.5.1.5 INTC_SIR_FIQ Register (offset = 44h) [reset = FFFFFF80h]
210
6.5.1.6 INTC_CONTROL Register (offset = 48h) [reset = 0h]
211
6.5.1.7 INTC_PROTECTION Register (offset = 4Ch) [reset = 0h]
212
6.5.1.8 INTC_IDLE Register (offset = 50h) [reset = 0h]
213
6.5.1.9 INTC_IRQ_PRIORITY Register (offset = 60h) [reset = FFFFFFC0h]
214
6.5.1.10 INTC_FIQ_PRIORITY Register (offset = 64h) [reset = FFFFFFC0h]
215
6.5.1.11 INTC_THRESHOLD Register (offset = 68h) [reset = FFh]
216
6.5.1.12 INTC_ITR0 Register (offset = 80h) [reset = 0h]
217
6.5.1.13 INTC_MIR0 Register (offset = 84h) [reset = FFFFFFFFh]
218
6.5.1.14 INTC_MIR_CLEAR0 Register (offset = 88h) [reset = 0h]
219
6.5.1.15 INTC_MIR_SET0 Register (offset = 8Ch) [reset = 0h]
220
6.5.1.16 INTC_ISR_SET0 Register (offset = 90h) [reset = 0h]
221
6.5.1.17 INTC_ISR_CLEAR0 Register (offset = 94h) [reset = 0h]
222
6.5.1.18 INTC_PENDING_IRQ0 Register (offset = 98h) [reset = 0h]
223
6.5.1.19 INTC_PENDING_FIQ0 Register (offset = 9Ch) [reset = 0h]
224
6.5.1.20 INTC_ITR1 Register (offset = A0h) [reset = 0h]
225
6.5.1.21 INTC_MIR1 Register (offset = A4h) [reset = FFFFFFFFh]
226
6.5.1.22 INTC_MIR_CLEAR1 Register (offset = A8h) [reset = 0h]
227
6.5.1.23 INTC_MIR_SET1 Register (offset = ACh) [reset = 0h]
228
6.5.1.24 INTC_ISR_SET1 Register (offset = B0h) [reset = 0h]
229
6.5.1.25 INTC_ISR_CLEAR1 Register (offset = B4h) [reset = 0h]
230
6.5.1.26 INTC_PENDING_IRQ1 Register (offset = B8h) [reset = 0h]
231
6.5.1.27 INTC_PENDING_FIQ1 Register (offset = BCh) [reset = 0h]
232
6.5.1.28 INTC_ITR2 Register (offset = C0h) [reset = 0h]
233
6.5.1.29 INTC_MIR2 Register (offset = C4h) [reset = FFFFFFFFh]
234
6.5.1.30 INTC_MIR_CLEAR2 Register (offset = C8h) [reset = 0h]
235
6.5.1.31 INTC_MIR_SET2 Register (offset = CCh) [reset = 0h]
236
6.5.1.32 INTC_ISR_SET2 Register (offset = D0h) [reset = 0h]
237
6.5.1.33 INTC_ISR_CLEAR2 Register (offset = D4h) [reset = 0h]
238
6.5.1.34 INTC_PENDING_IRQ2 Register (offset = D8h) [reset = 0h]
239
6.5.1.35 INTC_PENDING_FIQ2 Register (offset = DCh) [reset = 0h]
240
6.5.1.36 INTC_ITR3 Register (offset = E0h) [reset = 0h]
241
6.5.1.37 INTC_MIR3 Register (offset = E4h) [reset = FFFFFFFFh]
242
6.5.1.38 INTC_MIR_CLEAR3 Register (offset = E8h) [reset = 0h]
243
6.5.1.39 INTC_MIR_SET3 Register (offset = ECh) [reset = 0h]
244
6.5.1.40 INTC_ISR_SET3 Register (offset = F0h) [reset = 0h]
245
6.5.1.41 INTC_ISR_CLEAR3 Register (offset = F4h) [reset = 0h]
246
6.5.1.42 INTC_PENDING_IRQ3 Register (offset = F8h) [reset = 0h]
247
6.5.1.43 INTC_PENDING_FIQ3 Register (offset = FCh) [reset = 0h]
248
6.5.1.44 INTC_ILR Register (offset = 100h to 2FCh) [reset = 0h]
249
7 Memory Subsystem
250
7.1 GPMC
251
7.1.1 Introduction
251
7.1.1.1 GPMC Features
251
7.1.1.2 Block Diagram
252
7.1.1.3 Unsupported GPMC Features
253
7.1.2 Integration
254
7.1.2.1 GPMC Connectivity Attributes
254
7.1.2.2 GPMC Clock and Reset Management
254
7.1.2.3 GPMC Signal List
255
7.1.3 Functional Description
256
7.1.3.1 GPMC Signals
256
7.1.3.2 GPMC Modes
258
7.1.3.3 GPMC Functional Description
260
7.1.3.3.1 GPMC Clock Configuration
261
7.1.3.3.2 GPMC Software Reset
261
7.1.3.3.3 GPMC Power Management
261
7.1.3.3.4 GPMC Interrupt Requests
262
7.1.3.3.5 GPMC DMA Requests
262
7.1.3.3.6 L3 Slow Interconnect Interface
262
7.1.3.3.7 GPMC Address and Data Bus
263
7.1.3.3.8 Address Decoder and Chip-Select Configuration
263
7.1.3.3.9 Timing Setting
275
7.1.3.3.10 NOR Access Description
280
7.1.3.3.11 pSRAM Access Specificities
301
7.1.3.3.12 NAND Access Description
301
7.1.3.4 GPMC High-Level Programming Model Overview
335
7.1.3.5 GPMC Initialization
337
7.1.3.6 GPMC Configuration in NOR Mode
338
7.1.3.7 GPMC Configuration in NAND Mode
339
7.1.3.8 Set Memory Access
342
7.1.3.9 GPMC Timing Parameters
343
7.1.3.9.1 GPMC Timing Parameters Formulas
346
7.1.4 Use Cases
355
7.1.4.1 How to Set GPMC Timing Parameters for Typical Accesses
355
7.1.4.1.1 External Memory Attached to the GPMC Module
355
7.1.4.1.2 Typical GPMC Setup
355
7.1.4.1.3 GPMC Configuration for Synchronous Burst Read Access
357
7.1.4.1.4 GPMC Configuration for Asynchronous Read Access
359
7.1.4.1.5 GPMC Configuration for Asynchronous Single Write Access
361
7.1.4.2 How to Choose a Suitable Memory to Use With the GPMC
363
7.1.4.2.1 Supported Memories or Devices
363
7.1.4.2.2 NAND Interface Protocol
363
7.1.4.2.3 NOR Interface Protocol
363
7.1.4.2.4 Other Technologies
365
7.1.4.2.5 Supported Protocols
365
7.1.4.2.6 GPMC Features and Settings
365
7.1.5 Registers
366
7.1.5.1 GPMC_REVISION
367
7.1.5.2 GPMC_SYSCONFIG
367
7.1.5.3 GPMC_SYSSTATUS
368
7.1.5.4 GPMC_IRQSTATUS
369
7.1.5.5 GPMC_IRQENABLE
370
7.1.5.6 GPMC_TIMEOUT_CONTROL
371
7.1.5.7 GPMC_ERR_ADDRESS
371
7.1.5.8 GPMC_ERR_TYPE
372
7.1.5.9 GPMC_CONFIG
373
7.1.5.10 GPMC_STATUS
374
7.1.5.11 GPMC_CONFIG1_i
375
7.1.5.12 GPMC_CONFIG2_i
377
7.1.5.13 GPMC_CONFIG3_i
378
7.1.5.14 GPMC_CONFIG4_i
380
7.1.5.15 GPMC_CONFIG5_i
382
7.1.5.16 GPMC_CONFIG6_i
383
7.1.5.17 GPMC_CONFIG7_i
384
7.1.5.18 GPMC_NAND_COMMAND_i
385
7.1.5.19 GPMC_NAND_ADDRESS_i
385
7.1.5.20 GPMC_NAND_DATA_i
385
7.1.5.21 GPMC_PREFETCH_CONFIG1
386
7.1.5.22 GPMC_PREFETCH_CONFIG2
388
7.1.5.23 GPMC_PREFETCH_CONTROL
388
7.1.5.24 GPMC_PREFETCH_STATUS
389
7.1.5.25 GPMC_ECC_CONFIG
390
7.1.5.26 GPMC_ECC_CONTROL
391
7.1.5.27 GPMC_ECC_SIZE_CONFIG
392
7.1.5.28 GPMC_ECCj_RESULT
394
7.1.5.29 GPMC_BCH_RESULT0_i
395
7.1.5.30 GPMC_BCH_RESULT1_i
395
7.1.5.31 GPMC_BCH_RESULT2_i
395
7.1.5.32 GPMC_BCH_RESULT3_i
396
7.1.5.33 GPMC_BCH_SWDATA
396
7.1.5.34 GPMC_BCH_RESULT4_i
396
7.1.5.35 GPMC_BCH_RESULT5_i
397
7.1.5.36 GPMC_BCH_RESULT6_i
397
7.2 OCMC-RAM
398
7.2.1 Introduction
398
7.2.1.1 OCMC-RAM Features
398
7.2.1.2 Unsupported OCMC-RAM Features
398
7.2.2 Integration
399
7.2.2.1 OCMC RAM Connectivity Attributes
399
7.2.2.2 OCMC RAM Clock and Reset Management
399
7.2.2.3 OCMC RAM Pin List
399
7.3 EMIF
400
7.3.1 Introduction
400
7.3.1.1 Features
400
7.3.1.2 Unsupported EMIF Features
401
7.3.2 Integration
402
7.3.2.1 EMIF Connectivity Attributes
402
7.3.2.2 EMIF Clock Management
402
7.3.2.3 EMIF Pin List
402
7.3.3 Functional Description
404
7.3.3.1 Signal Descriptions
404
7.3.3.2 Clock Control
405
7.3.3.3 DDR2/3/mDDR Memory Controller Subsytem Overview
405
7.3.3.3.1 DDR2/3/mDDR Memory Controller Interface
406
7.3.3.3.2 Data Macro
407
7.3.3.3.3 Command Macro
408
7.3.3.3.4 VTP Controller Macro
408
7.3.3.3.5 DQS-Gate IOs
409
7.3.3.4 Address Mapping
409
7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
410
7.3.3.4.2 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 0
411
7.3.3.4.3 Address Mapping when REG_IBANK_POS=2 and REG_EBANK_POS = 0
411
7.3.3.4.4 Address Mapping when REG_IBANK_POS= 3 and REG_EBANK_POS = 0
411
7.3.3.4.5 Address Mapping when REG_IBANK_POS = 0 and REG_EBANK_POS = 1
412
7.3.3.4.6 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 1
412
7.3.3.4.7 Address Mapping when REG_IBANK_POS = 2 and REG_EBANK_POS = 1
413
7.3.3.4.8 Address Mapping when REG_IBANK_POS = 3 and REG_EBANK_POS = 1
413
7.3.3.5 Performance Management
414
7.3.3.5.1 Command Ordering and Scheduling
414
7.3.3.5.2 Command Starvation
415
7.3.3.5.3 Possible Race Condition
415
7.3.3.5.4 Class of Service (COS)
415
7.3.3.5.5 Refresh Scheduling
416
7.3.3.5.6 Performance Counter Configuration
417
7.3.3.6 DDR3 Read-Write Leveling
417
7.3.3.7 PRCM Sequence for DDR2/3/mDDR Memory controller
418
7.3.3.8 Interrupt Support
418
7.3.3.9 EDMA Event Support
418
7.3.3.10 Emulation Considerations
418
7.3.3.11 Power Management
419
7.3.3.11.1 Clock Stop Mode
419
7.3.3.11.2 Self-Refresh Mode
419
7.3.3.11.3 Power Down Mode
420
7.3.3.11.4 Deep Power-Down Mode
421
7.3.3.11.5 Save and Restore Mode
421
7.3.3.11.6 EMIF PHY Clock Gating
422
7.3.4 Use Cases
422
7.3.5 EMIF4D Registers
422
7.3.5.1 EMIF_MOD_ID_REV Register (offset = 0h) [reset = 40440C03h]
424
7.3.5.2 STATUS Register (offset = 4h) [reset = 0h]
425
7.3.5.3 SDRAM_CONFIG Register (offset = 8h) [reset = 0h]
426
7.3.5.4 SDRAM_CONFIG_2 Register (offset = Ch) [reset = 0h]
428
7.3.5.5 SDRAM_REF_CTRL Register (offset = 10h) [reset = 0h]
429
7.3.5.6 SDRAM_REF_CTRL_SHDW Register (offset = 14h) [reset = 0h]
430
7.3.5.7 SDRAM_TIM_1 Register (offset = 18h) [reset = 0h]
431
7.3.5.8 SDRAM_TIM_1_SHDW Register (offset = 1Ch) [reset = 0h]
432
7.3.5.9 SDRAM_TIM_2 Register (offset = 20h) [reset = 0h]
433
7.3.5.10 SDRAM_TIM_2_SHDW Register (offset = 24h) [reset = 0h]
434
7.3.5.11 SDRAM_TIM_3 Register (offset = 28h) [reset = 0h]
435
7.3.5.12 SDRAM_TIM_3_SHDW Register (offset = 2Ch) [reset = 0h]
436
7.3.5.13 PWR_MGMT_CTRL Register (offset = 38h) [reset = 0h]
437
7.3.5.14 PWR_MGMT_CTRL_SHDW Register (offset = 3Ch) [reset = 0h]
439
7.3.5.15 INT_CONFIG Register (offset = 54h) [reset = 0h]
440
7.3.5.16 INT_CFG_VAL_1 Register (offset = 58h) [reset = 0h]
441
7.3.5.17 INT_CFG_VAL_2 Register (offset = 5Ch) [reset = 0h]
442
7.3.5.18 PERF_CNT_1 Register (offset = 80h) [reset = 0h]
443
7.3.5.19 PERF_CNT_2 Register (offset = 84h) [reset = 0h]
444
7.3.5.20 PERF_CNT_CFG Register (offset = 88h) [reset = 10000h]
445
7.3.5.21 PERF_CNT_SEL Register (offset = 8Ch) [reset = 0h]
446
7.3.5.22 PERF_CNT_TIM Register (offset = 90h) [reset = 0h]
447
7.3.5.23 READ_IDLE_CTRL Register (offset = 98h) [reset = 50000h]
448
7.3.5.24 READ_IDLE_CTRL_SHDW Register (offset = 9Ch) [reset = 50000h]
449
7.3.5.25 IRQSTATUS_RAW_SYS Register (offset = A4h) [reset = 0h]
450
7.3.5.26 IRQSTATUS_SYS Register (offset = ACh) [reset = 0h]
451
7.3.5.27 IRQENABLE_SET_SYS Register (offset = B4h) [reset = 0h]
452
7.3.5.28 IRQENABLE_CLR_SYS Register (offset = BCh) [reset = 0h]
453
7.3.5.29 ZQ_CONFIG Register (offset = C8h) [reset = 0h]
454
7.3.5.30 RDWR_LVL_RMP_WIN Register (offset = D4h) [reset = 0h]
455
7.3.5.31 RDWR_LVL_RMP_CTRL Register (offset = D8h) [reset = 0h]
456
7.3.5.32 RDWR_LVL_CTRL Register (offset = DCh) [reset = 0h]
457
7.3.5.33 DDR_PHY_CTRL_1 Register (offset = E4h) [reset = 0h]
458
7.3.5.34 DDR_PHY_CTRL_1_SHDW Register (offset = E8h) [reset = 0h]
460
7.3.5.35 PRI_COS_MAP Register (offset = 100h) [reset = 0h]
462
7.3.5.36 CONNID_COS_1_MAP Register (offset = 104h) [reset = 0h]
463
7.3.5.37 CONNID_COS_2_MAP Register (offset = 108h) [reset = 0h]
464
7.3.5.38 RD_WR_EXEC_THRSH Register (offset = 120h) [reset = 0h]
466
7.3.6 DDR2/3/mDDR PHY Registers
467
7.3.6.1 DDR PHY Command 0/1/2 Address/Command Slave Ratio Register (CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
469
7.3.6.2 DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register( CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
469
7.3.6.3 DDR PHY Command 0/1/2 Invert Clockout Selection Register( CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
470
7.3.6.4 DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register (DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)
470
7.3.6.5 DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register (DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
471
7.3.6.6 DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register ( DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
471
7.3.6.7 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register (DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
472
7.3.6.8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register (DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
472
7.3.6.9 DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register (DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
473
7.3.6.10 DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register (DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
473
7.3.6.11 DDR PHY Data Macro 0/1 Write Data Slave Ratio Register (DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
474
7.3.6.12 DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
475
7.4 ELM
476
7.4.1 Introduction
476
7.4.1.1 ELM Features
476
7.4.1.2 Unsupported ELM Features
476
7.4.2 Integration
477
7.4.2.1 ELM Connectivity Attributes
477
7.4.2.2 ELM Clock and Reset Management
477
7.4.2.3 ELM Pin List
477
7.4.3 Functional Description
478
7.4.3.1 ELM Software Reset
478
7.4.3.2 ELM Power Management
478
7.4.3.3 ELM Interrupt Requests
478
7.4.3.4 Processing Initialization
479
7.4.3.5 Processing Sequence
479
7.4.3.6 Processing Completion
480
7.4.4 Basic Programming Model
481
7.4.4.1 ELM Low Level Programming Model
481
7.4.4.1.1 Processing Initialization
481
7.4.4.1.2 Read Results
481
7.4.4.2 Use Case: ELM Used in Continuous Mode
482
7.4.4.3 Use Case: ELM Used in Page Mode
484
7.4.5 ELM Registers
487
7.4.5.1 ELM Revision Register (ELM_REVISION)
488
7.4.5.2 ELM System Configuration Register (ELM_SYSCONFIG)
488
7.4.5.3 ELM System Status Register (ELM_SYSSTATUS)
489
7.4.5.4 ELM Interrupt Status Register (ELM_IRQSTATUS)
490
7.4.5.5 ELM Interrupt Enable Register (ELM_IRQENABLE)
492
7.4.5.6 ELM Location Configuration Register (ELM_LOCATION_CONFIG)
493
7.4.5.7 ELM Page Definition Register (ELM_PAGE_CTRL)
494
7.4.5.8 ELM_SYNDROME_FRAGMENT_0_i Register
495
7.4.5.9 ELM_SYNDROME_FRAGMENT_1_i Register
495
7.4.5.10 ELM_SYNDROME_FRAGMENT_2_i Register
495
7.4.5.11 ELM_SYNDROME_FRAGMENT_3_i Register
496
7.4.5.12 ELM_SYNDROME_FRAGMENT_4_i Register
496
7.4.5.13 ELM_SYNDROME_FRAGMENT_5_i Register
496
7.4.5.14 ELM_SYNDROME_FRAGMENT_6_i Register
497
7.4.5.15 ELM_LOCATION_STATUS_i Register
497
7.4.5.16 ELM_ERROR_LOCATION_0-15_i Registers
498
8 Power, Reset, and Clock Management (PRCM)
499
8.1 Power, Reset, and Clock Management
500
8.1.1 Introduction
500
8.1.2 Device Power-Management Architecture Building Blocks
500
8.1.3 Clock Management
500
8.1.3.1 Module Interface and Functional Clocks
500
8.1.3.2 Module-Level Clock Management
501
8.1.3.2.1 Master Standby Protocol
501
8.1.3.2.2 Slave Idle Protocol
502
8.1.3.3 Clock Domain
504
8.1.3.3.1 Clock Domain-Level Clock Management
505
8.1.4 Power Management
506
8.1.4.1 Power Domain
506
8.1.4.2 Power Domain Management
508
8.1.4.2.1 Power-Management Techniques
508
8.1.4.3 Power Modes
509
8.1.4.3.1 Active
510
8.1.4.3.2 Standby
510
8.1.4.3.3 Deepsleep1
511
8.1.4.3.4 Deepsleep0
511
8.1.4.3.5 RTC-Only
511
8.1.4.3.6 Internal RTC LDO
512
8.1.4.3.7 Supported Low Power USB Wakeup Scenarios
513
8.1.4.4 Main Oscillator Control During Deep Sleep
513
8.1.4.5 Wakeup Sources/Events
514
8.1.4.6 Functional Sequencing for Power Management with Cortex M3
514
8.1.4.6.1 Periodic Idling of Cortex A8 MPU
517
8.1.4.6.2 Sleep Sequencing
517
8.1.4.6.3 Wakeup Sequencing
517
8.1.5 PRCM Module Overview
517
8.1.5.1 Interface Descriptions
518
8.1.5.1.1 OCP Interfaces
518
8.1.5.1.2 OCP Slave Interfaces
518
8.1.5.1.3 Power Control Interface
518
8.1.5.1.4 Device Control Interface
518
8.1.5.1.5 Clocks Interface
519
8.1.5.1.6 Resets Interface
519
8.1.5.1.7 Modules Power Management Control Interface
519
8.1.5.1.8 Initiator Modules Interface
519
8.1.5.1.9 Targets Modules Interface
519
8.1.6 Clock Generation and Management
519
8.1.6.1 Terminology
519
8.1.6.2 Clock Structure
519
8.1.6.3 ADPLLS
520
8.1.6.3.1 Clock Functions
521
8.1.6.4 ADPLLLJ (Low Jitter DPLL)
521
8.1.6.4.1 Clock Functions
523
8.1.6.5 M2 and N2 Change On-the-Fly
523
8.1.6.6 Spread Spectrum Clocking (SSC)
523
8.1.6.7 Core PLL Description
524
8.1.6.7.1 Core PLL Configuration
527
8.1.6.8 Peripheral PLL Description
527
8.1.6.8.1 Configuring the Peripheral PLL
529
8.1.6.9 MPU PLL Description
529
8.1.6.9.1 Configuring the MPU PLL
530
8.1.6.10 Display PLL Description
531
8.1.6.10.1 Configuring the Display PLL
531
8.1.6.11 DDR PLL Description
532
8.1.6.11.1 Configuring the DDR PLL
532
8.1.6.12 CLKOUT Signals
533
8.1.6.13 Timer Clock Structure
533
8.1.7 Reset Management
535
8.1.7.1 Overview
535
8.1.7.2 Reset Concepts and Definitions
535
8.1.7.3 Global Power On Reset (Cold Reset)
536
8.1.7.3.1 Power On Reset (PORz)
536
8.1.7.3.2 PORz Sequence
536
8.1.7.3.3 Bad Device Reset
537
8.1.7.3.4 Global Cold Software Reset (GLOBAL_COLD_SW_RST)
537
8.1.7.4 Global Warm Reset
537
8.1.7.4.1 External Warm Reset
537
8.1.7.4.2 Watchdog Timer
540
8.1.7.4.3 Global Warm Software Reset (GLOBAL_SW_WARM_RST)
540
8.1.7.4.4 Test Reset (TRSTz)
540
8.1.7.5 Reset Characteristics
541
8.1.7.6 EMAC Switch Reset Isolation
543
8.1.7.7 Reset Priority
543
8.1.7.8 Trace Functionality Across Reset
543
8.1.7.9 RTC PORz
543
8.1.8 Power-Up/Down Sequence
544
8.1.9 IO State
544
8.1.10 Voltage and Power Domains
544
8.1.10.1 Voltage Domains
545
8.1.10.2 Power Domains
545
8.1.11 Device Modules and Power Management Attributes List
545
8.1.11.1 Power Domain Power Down Sequence
547
8.1.11.2 Power Domain Power-Up Sequence
547
8.1.12 Clock Module Registers
548
8.1.12.1 CM_PER Registers
548
8.1.12.1.1 CM_PER_L4LS_CLKSTCTRL Register (offset = 0h) [reset = C0102h]
550
8.1.12.1.2 CM_PER_L3S_CLKSTCTRL Register (offset = 4h) [reset = Ah]
552
8.1.12.1.3 CM_PER_L4FW_CLKSTCTRL Register (offset = 8h) [reset = 102h]
553
8.1.12.1.4 CM_PER_L3_CLKSTCTRL Register (offset = Ch) [reset = 12h]
554
8.1.12.1.5 CM_PER_CPGMAC0_CLKCTRL Register (offset = 14h) [reset = 70000h]
555
8.1.12.1.6 CM_PER_LCDC_CLKCTRL Register (offset = 18h) [reset = 70000h]
556
8.1.12.1.7 CM_PER_USB0_CLKCTRL Register (offset = 1Ch) [reset = 70000h]
557
8.1.12.1.8 CM_PER_TPTC0_CLKCTRL Register (offset = 24h) [reset = 70000h]
558
8.1.12.1.9 CM_PER_EMIF_CLKCTRL Register (offset = 28h) [reset = 30000h]
559
8.1.12.1.10 CM_PER_OCMCRAM_CLKCTRL Register (offset = 2Ch) [reset = 30000h]
560
8.1.12.1.11 CM_PER_GPMC_CLKCTRL Register (offset = 30h) [reset = 30002h]
561
8.1.12.1.12 CM_PER_MCASP0_CLKCTRL Register (offset = 34h) [reset = 30000h]
562
8.1.12.1.13 CM_PER_UART5_CLKCTRL Register (offset = 38h) [reset = 30000h]
563
8.1.12.1.14 CM_PER_MMC0_CLKCTRL Register (offset = 3Ch) [reset = 30000h]
564
8.1.12.1.15 CM_PER_ELM_CLKCTRL Register (offset = 40h) [reset = 30000h]
565
8.1.12.1.16 CM_PER_I2C2_CLKCTRL Register (offset = 44h) [reset = 30000h]
566
8.1.12.1.17 CM_PER_I2C1_CLKCTRL Register (offset = 48h) [reset = 30000h]
567
8.1.12.1.18 CM_PER_SPI0_CLKCTRL Register (offset = 4Ch) [reset = 30000h]
568
8.1.12.1.19 CM_PER_SPI1_CLKCTRL Register (offset = 50h) [reset = 30000h]
569
8.1.12.1.20 CM_PER_L4LS_CLKCTRL Register (offset = 60h) [reset = 2h]
570
8.1.12.1.21 CM_PER_L4FW_CLKCTRL Register (offset = 64h) [reset = 2h]
571
8.1.12.1.22 CM_PER_MCASP1_CLKCTRL Register (offset = 68h) [reset = 30000h]
572
8.1.12.1.23 CM_PER_UART1_CLKCTRL Register (offset = 6Ch) [reset = 30000h]
573
8.1.12.1.24 CM_PER_UART2_CLKCTRL Register (offset = 70h) [reset = 30000h]
574
8.1.12.1.25 CM_PER_UART3_CLKCTRL Register (offset = 74h) [reset = 30000h]
575
8.1.12.1.26 CM_PER_UART4_CLKCTRL Register (offset = 78h) [reset = 30000h]
576
8.1.12.1.27 CM_PER_TIMER7_CLKCTRL Register (offset = 7Ch) [reset = 30000h]
577
8.1.12.1.28 CM_PER_TIMER2_CLKCTRL Register (offset = 80h) [reset = 30000h]
578
8.1.12.1.29 CM_PER_TIMER3_CLKCTRL Register (offset = 84h) [reset = 30000h]
579
8.1.12.1.30 CM_PER_TIMER4_CLKCTRL Register (offset = 88h) [reset = 30000h]
580
8.1.12.1.31 CM_PER_GPIO1_CLKCTRL Register (offset = ACh) [reset = 30000h]
581
8.1.12.1.32 CM_PER_GPIO2_CLKCTRL Register (offset = B0h) [reset = 30000h]
582
8.1.12.1.33 CM_PER_GPIO3_CLKCTRL Register (offset = B4h) [reset = 30000h]
583
8.1.12.1.34 CM_PER_TPCC_CLKCTRL Register (offset = BCh) [reset = 30000h]
584
8.1.12.1.35 CM_PER_DCAN0_CLKCTRL Register (offset = C0h) [reset = 30000h]
585
8.1.12.1.36 CM_PER_DCAN1_CLKCTRL Register (offset = C4h) [reset = 30000h]
586
8.1.12.1.37 CM_PER_EPWMSS1_CLKCTRL Register (offset = CCh) [reset = 30000h]
587
8.1.12.1.38 CM_PER_EMIF_FW_CLKCTRL Register (offset = D0h) [reset = 30000h]
588
8.1.12.1.39 CM_PER_EPWMSS0_CLKCTRL Register (offset = D4h) [reset = 30000h]
589
8.1.12.1.40 CM_PER_EPWMSS2_CLKCTRL Register (offset = D8h) [reset = 30000h]
590
8.1.12.1.41 CM_PER_L3_INSTR_CLKCTRL Register (offset = DCh) [reset = 2h]
591
8.1.12.1.42 CM_PER_L3_CLKCTRL Register (offset = E0h) [reset = 2h]
592
8.1.12.1.43 CM_PER_IEEE5000_CLKCTRL Register (offset = E4h) [reset = 70002h]
593
8.1.12.1.44 CM_PER_PRU_ICSS_CLKCTRL Register (offset = E8h) [reset = 70000h]
594
8.1.12.1.45 CM_PER_TIMER5_CLKCTRL Register (offset = ECh) [reset = 30000h]
595
8.1.12.1.46 CM_PER_TIMER6_CLKCTRL Register (offset = F0h) [reset = 30000h]
596
8.1.12.1.47 CM_PER_MMC1_CLKCTRL Register (offset = F4h) [reset = 30000h]
597
8.1.12.1.48 CM_PER_MMC2_CLKCTRL Register (offset = F8h) [reset = 30000h]
598
8.1.12.1.49 CM_PER_TPTC1_CLKCTRL Register (offset = FCh) [reset = 70000h]
599
8.1.12.1.50 CM_PER_TPTC2_CLKCTRL Register (offset = 100h) [reset = 70000h]
600
8.1.12.1.51 CM_PER_SPINLOCK_CLKCTRL Register (offset = 10Ch) [reset = 30000h]
601
8.1.12.1.52 CM_PER_MAILBOX0_CLKCTRL Register (offset = 110h) [reset = 30000h]
602
8.1.12.1.53 CM_PER_L4HS_CLKSTCTRL Register (offset = 11Ch) [reset = 7Ah]
603
8.1.12.1.54 CM_PER_L4HS_CLKCTRL Register (offset = 120h) [reset = 2h]
604
8.1.12.1.55 CM_PER_OCPWP_L3_CLKSTCTRL Register (offset = 12Ch) [reset = 2h]
605
8.1.12.1.56 CM_PER_OCPWP_CLKCTRL Register (offset = 130h) [reset = 70002h]
606
8.1.12.1.57 CM_PER_PRU_ICSS_CLKSTCTRL Register (offset = 140h) [reset = 2h]
607
8.1.12.1.58 CM_PER_CPSW_CLKSTCTRL Register (offset = 144h) [reset = 2h]
608
8.1.12.1.59 CM_PER_LCDC_CLKSTCTRL Register (offset = 148h) [reset = 2h]
609
8.1.12.1.60 CM_PER_CLKDIV32K_CLKCTRL Register (offset = 14Ch) [reset = 30000h]
610
8.1.12.1.61 CM_PER_CLK_24MHZ_CLKSTCTRL Register (offset = 150h) [reset = 2h]
611
8.1.12.2 CM_WKUP Registers
611
8.1.12.2.1 CM_WKUP_CLKSTCTRL Register (offset = 0h) [reset = 6h]
615
8.1.12.2.2 CM_WKUP_CONTROL_CLKCTRL Register (offset = 4h) [reset = 30000h]
617
8.1.12.2.3 CM_WKUP_GPIO0_CLKCTRL Register (offset = 8h) [reset = 30000h]
618
8.1.12.2.4 CM_WKUP_L4WKUP_CLKCTRL Register (offset = Ch) [reset = 2h]
619
8.1.12.2.5 CM_WKUP_TIMER0_CLKCTRL Register (offset = 10h) [reset = 30002h]
620
8.1.12.2.6 CM_WKUP_DEBUGSS_CLKCTRL Register (offset = 14h) [reset = 52580002h]
621
8.1.12.2.7 CM_L3_AON_CLKSTCTRL Register (offset = 18h) [reset = 1Ah]
622
8.1.12.2.8 CM_AUTOIDLE_DPLL_MPU Register (offset = 1Ch) [reset = 0h]
623
8.1.12.2.9 CM_IDLEST_DPLL_MPU Register (offset = 20h) [reset = 0h]
624
8.1.12.2.10 CM_SSC_DELTAMSTEP_DPLL_MPU Register (offset = 24h) [reset = 0h]
625
8.1.12.2.11 CM_SSC_MODFREQDIV_DPLL_MPU Register (offset = 28h) [reset = 0h]
626
8.1.12.2.12 CM_CLKSEL_DPLL_MPU Register (offset = 2Ch) [reset = 0h]
627
8.1.12.2.13 CM_AUTOIDLE_DPLL_DDR Register (offset = 30h) [reset = 0h]
628
8.1.12.2.14 CM_IDLEST_DPLL_DDR Register (offset = 34h) [reset = 0h]
629
8.1.12.2.15 CM_SSC_DELTAMSTEP_DPLL_DDR Register (offset = 38h) [reset = 0h]
630
8.1.12.2.16 CM_SSC_MODFREQDIV_DPLL_DDR Register (offset = 3Ch) [reset = 0h]
631
8.1.12.2.17 CM_CLKSEL_DPLL_DDR Register (offset = 40h) [reset = 0h]
632
8.1.12.2.18 CM_AUTOIDLE_DPLL_DISP Register (offset = 44h) [reset = 0h]
633
8.1.12.2.19 CM_IDLEST_DPLL_DISP Register (offset = 48h) [reset = 0h]
634
8.1.12.2.20 CM_SSC_DELTAMSTEP_DPLL_DISP Register (offset = 4Ch) [reset = 0h]
635
8.1.12.2.21 CM_SSC_MODFREQDIV_DPLL_DISP Register (offset = 50h) [reset = 0h]
636
8.1.12.2.22 CM_CLKSEL_DPLL_DISP Register (offset = 54h) [reset = 0h]
637
8.1.12.2.23 CM_AUTOIDLE_DPLL_CORE Register (offset = 58h) [reset = 0h]
638
8.1.12.2.24 CM_IDLEST_DPLL_CORE Register (offset = 5Ch) [reset = 0h]
639
8.1.12.2.25 CM_SSC_DELTAMSTEP_DPLL_CORE Register (offset = 60h) [reset = 0h]
640
8.1.12.2.26 CM_SSC_MODFREQDIV_DPLL_CORE Register (offset = 64h) [reset = 0h]
641
8.1.12.2.27 CM_CLKSEL_DPLL_CORE Register (offset = 68h) [reset = 0h]
642
8.1.12.2.28 CM_AUTOIDLE_DPLL_PER Register (offset = 6Ch) [reset = 0h]
643
8.1.12.2.29 CM_IDLEST_DPLL_PER Register (offset = 70h) [reset = 0h]
644
8.1.12.2.30 CM_SSC_DELTAMSTEP_DPLL_PER Register (offset = 74h) [reset = 0h]
645
8.1.12.2.31 CM_SSC_MODFREQDIV_DPLL_PER Register (offset = 78h) [reset = 0h]
646
8.1.12.2.32 CM_CLKDCOLDO_DPLL_PER Register (offset = 7Ch) [reset = 0h]
647
8.1.12.2.33 CM_DIV_M4_DPLL_CORE Register (offset = 80h) [reset = 4h]
648
8.1.12.2.34 CM_DIV_M5_DPLL_CORE Register (offset = 84h) [reset = 4h]
649
8.1.12.2.35 CM_CLKMODE_DPLL_MPU Register (offset = 88h) [reset = 4h]
650
8.1.12.2.36 CM_CLKMODE_DPLL_PER Register (offset = 8Ch) [reset = 4h]
652
8.1.12.2.37 CM_CLKMODE_DPLL_CORE Register (offset = 90h) [reset = 4h]
653
8.1.12.2.38 CM_CLKMODE_DPLL_DDR Register (offset = 94h) [reset = 4h]
655
8.1.12.2.39 CM_CLKMODE_DPLL_DISP Register (offset = 98h) [reset = 4h]
657
8.1.12.2.40 CM_CLKSEL_DPLL_PERIPH Register (offset = 9Ch) [reset = 0h]
659
8.1.12.2.41 CM_DIV_M2_DPLL_DDR Register (offset = A0h) [reset = 1h]
660
8.1.12.2.42 CM_DIV_M2_DPLL_DISP Register (offset = A4h) [reset = 1h]
661
8.1.12.2.43 CM_DIV_M2_DPLL_MPU Register (offset = A8h) [reset = 1h]
662
8.1.12.2.44 CM_DIV_M2_DPLL_PER Register (offset = ACh) [reset = 1h]
663
8.1.12.2.45 CM_WKUP_WKUP_M3_CLKCTRL Register (offset = B0h) [reset = 2h]
664
8.1.12.2.46 CM_WKUP_UART0_CLKCTRL Register (offset = B4h) [reset = 30000h]
665
8.1.12.2.47 CM_WKUP_I2C0_CLKCTRL Register (offset = B8h) [reset = 30000h]
666
8.1.12.2.48 CM_WKUP_ADC_TSC_CLKCTRL Register (offset = BCh) [reset = 30000h]
667
8.1.12.2.49 CM_WKUP_SMARTREFLEX0_CLKCTRL Register (offset = C0h) [reset = 30000h]
668
8.1.12.2.50 CM_WKUP_TIMER1_CLKCTRL Register (offset = C4h) [reset = 30000h]
669
8.1.12.2.51 CM_WKUP_SMARTREFLEX1_CLKCTRL Register (offset = C8h) [reset = 30000h]
670
8.1.12.2.52 CM_L4_WKUP_AON_CLKSTCTRL Register (offset = CCh) [reset = 6h]
671
8.1.12.2.53 CM_WKUP_WDT1_CLKCTRL Register (offset = D4h) [reset = 30002h]
672
8.1.12.2.54 CM_DIV_M6_DPLL_CORE Register (offset = D8h) [reset = 4h]
673
8.1.12.3 CM_DPLL Registers
673
8.1.12.3.1 CLKSEL_TIMER7_CLK Register (offset = 4h) [reset = 1h]
675
8.1.12.3.2 CLKSEL_TIMER2_CLK Register (offset = 8h) [reset = 1h]
676
8.1.12.3.3 CLKSEL_TIMER3_CLK Register (offset = Ch) [reset = 1h]
677
8.1.12.3.4 CLKSEL_TIMER4_CLK Register (offset = 10h) [reset = 1h]
678
8.1.12.3.5 CM_MAC_CLKSEL Register (offset = 14h) [reset = 4h]
679
8.1.12.3.6 CLKSEL_TIMER5_CLK Register (offset = 18h) [reset = 1h]
680
8.1.12.3.7 CLKSEL_TIMER6_CLK Register (offset = 1Ch) [reset = 1h]
681
8.1.12.3.8 CM_CPTS_RFT_CLKSEL Register (offset = 20h) [reset = 0h]
682
8.1.12.3.9 CLKSEL_TIMER1MS_CLK Register (offset = 28h) [reset = 0h]
683
8.1.12.3.10 CLKSEL_GFX_FCLK Register (offset = 2Ch) [reset = 0h]
684
8.1.12.3.11 CLKSEL_PRU_ICSS_OCP_CLK Register (offset = 30h) [reset = 0h]
685
8.1.12.3.12 CLKSEL_LCDC_PIXEL_CLK Register (offset = 34h) [reset = 0h]
686
8.1.12.3.13 CLKSEL_WDT1_CLK Register (offset = 38h) [reset = 1h]
687
8.1.12.3.14 CLKSEL_GPIO0_DBCLK Register (offset = 3Ch) [reset = 0h]
688
8.1.12.4 CM_MPU Registers
688
8.1.12.4.1 CM_MPU_CLKSTCTRL Register (offset = 0h) [reset = 6h]
689
8.1.12.4.2 CM_MPU_MPU_CLKCTRL Register (offset = 4h) [reset = 2h]
690
8.1.12.5 CM_DEVICE Registers
690
8.1.12.5.1 CM_CLKOUT_CTRL Register (offset = 0h) [reset = 0h]
692
8.1.12.6 CM_RTC Registers
692
8.1.12.6.1 CM_RTC_RTC_CLKCTRL Register (offset = 0h) [reset = 30002h]
694
8.1.12.6.2 CM_RTC_CLKSTCTRL Register (offset = 4h) [reset = 102h]
695
8.1.12.7 CM_GFX Registers
695
8.1.12.7.1 CM_GFX_L3_CLKSTCTRL Register (offset = 0h) [reset = 2h]
697
8.1.12.7.2 CM_GFX_GFX_CLKCTRL Register (offset = 4h) [reset = 70000h]
698
8.1.12.7.3 CM_GFX_L4LS_GFX_CLKSTCTRL Register (offset = Ch) [reset = 102h]
699
8.1.12.7.4 CM_GFX_MMUCFG_CLKCTRL Register (offset = 10h) [reset = 30000h]
700
8.1.12.7.5 CM_GFX_MMUDATA_CLKCTRL Register (offset = 14h) [reset = 30000h]
701
8.1.12.8 CM_CEFUSE Registers
701
8.1.12.8.1 CM_CEFUSE_CLKSTCTRL Register (offset = 0h) [reset = 2h]
703
8.1.12.8.2 CM_CEFUSE_CEFUSE_CLKCTRL Register (offset = 20h) [reset = 30000h]
704
8.1.13 Power Management Registers
705
8.1.13.1 PRM_IRQ Registers
705
8.1.13.1.1 REVISION_PRM Register (offset = 0h) [reset = 0h]
706
8.1.13.1.2 PRM_IRQSTATUS_MPU Register (offset = 4h) [reset = 0h]
707
8.1.13.1.3 PRM_IRQENABLE_MPU Register (offset = 8h) [reset = 0h]
708
8.1.13.1.4 PRM_IRQSTATUS_M3 Register (offset = Ch) [reset = 0h]
709
8.1.13.1.5 PRM_IRQENABLE_M3 Register (offset = 10h) [reset = 0h]
710
8.1.13.2 PRM_PER Registers
711
8.1.13.2.1 RM_PER_RSTCTRL Register (offset = 0h) [reset = 2h]
712
8.1.13.2.2 PM_PER_PWRSTST Register (offset = 8h) [reset = 1E60007h]
713
8.1.13.2.3 PM_PER_PWRSTCTRL Register (offset = Ch) [reset = EE0000EBh]
714
8.1.13.3 PRM_WKUP Registers
715
8.1.13.3.1 RM_WKUP_RSTCTRL Register (offset = 0h) [reset = 8h]
716
8.1.13.3.2 PM_WKUP_PWRSTCTRL Register (offset = 4h) [reset = 8h]
717
8.1.13.3.3 PM_WKUP_PWRSTST Register (offset = 8h) [reset = 60004h]
718
8.1.13.3.4 RM_WKUP_RSTST Register (offset = Ch) [reset = 0h]
719
8.1.13.4 PRM_MPU Registers
719
8.1.13.4.1 PM_MPU_PWRSTCTRL Register (offset = 0h) [reset = 1FF0007h]
721
8.1.13.4.2 PM_MPU_PWRSTST Register (offset = 4h) [reset = 157h]
723
8.1.13.4.3 RM_MPU_RSTST Register (offset = 8h) [reset = 0h]
724
8.1.13.5 PRM_DEVICE Registers
724
8.1.13.5.1 PRM_RSTCTRL Register (offset = 0h) [reset = 0h]
726
8.1.13.5.2 PRM_RSTTIME Register (offset = 4h) [reset = 1006h]
727
8.1.13.5.3 PRM_RSTST Register (offset = 8h) [reset = 1h]
728
8.1.13.5.4 PRM_SRAM_COUNT Register (offset = Ch) [reset = 78000017h]
729
8.1.13.5.5 PRM_LDO_SRAM_CORE_SETUP Register (offset = 10h) [reset = 0h]
730
8.1.13.5.6 PRM_LDO_SRAM_CORE_CTRL Register (offset = 14h) [reset = 0h]
732
8.1.13.5.7 PRM_LDO_SRAM_MPU_SETUP Register (offset = 18h) [reset = 0h]
733
8.1.13.5.8 PRM_LDO_SRAM_MPU_CTRL Register (offset = 1Ch) [reset = 0h]
735
8.1.13.6 PRM_RTC Registers
735
8.1.13.6.1 PM_RTC_PWRSTCTRL Register (offset = 0h) [reset = 4h]
737
8.1.13.6.2 PM_RTC_PWRSTST Register (offset = 4h) [reset = 4h]
738
8.1.13.7 PRM_GFX Registers
738
8.1.13.7.1 PM_GFX_PWRSTCTRL Register (offset = 0h) [reset = 60044h]
740
8.1.13.7.2 RM_GFX_RSTCTRL Register (offset = 4h) [reset = 1h]
741
8.1.13.7.3 PM_GFX_PWRSTST Register (offset = 10h) [reset = 17h]
742
8.1.13.7.4 RM_GFX_RSTST Register (offset = 14h) [reset = 0h]
743
8.1.13.8 PRM_CEFUSE Registers
743
8.1.13.8.1 PM_CEFUSE_PWRSTCTRL Register (offset = 0h) [reset = 0h]
744
8.1.13.8.2 PM_CEFUSE_PWRSTST Register (offset = 4h) [reset = 7h]
745
9 Control Module
746
9.1 Introduction
747
9.2 Functional Description
747
9.2.1 Control Module Initialization
747
9.2.2 Pad Control Registers
747
9.2.2.1 Mode Selection
748
9.2.2.2 Pull Selection
748
9.2.2.3 RX Active
748
9.2.3 EDMA Event Multiplexing
748
9.2.4 Device Control and Status
749
9.2.4.1 Control and Boot Status
749
9.2.4.2 Interprocessor Communication
749
9.2.4.3 Initiator Priority Control
750
9.2.4.3.1 Initiator Priority Control for Interconnect
750
9.2.4.3.2 Initiator Priority at EMIF
750
9.2.4.4 Peripheral Control and Status
750
9.2.4.4.1 USB Control and Status
750
9.2.4.4.2 USB Charger Detect
750
9.2.4.4.3 Ethernet MII Mode Selection
752
9.2.4.4.4 Ethernet Module Reset Isolation Control
752
9.2.4.4.5 Timer/eCAP Event Capture Control
753
9.2.4.4.6 ADC Capture Control
755
9.2.5 DDR PHY
756
9.2.5.1 DDR PHY to IO Pin Mapping
756
9.3 CONTROL_MODULE Registers
757
9.3.1 control_revision Register (offset = 0h) [reset = 0h]
762
9.3.2 control_hwinfo Register (offset = 4h) [reset = 0h]
763
9.3.3 control_sysconfig Register (offset = 10h) [reset = 0h]
764
9.3.4 control_status Register (offset = 40h) [reset = 0h]
765
9.3.5 control_emif_sdram_config Register (offset = 110h) [reset = 0h]
766
9.3.6 core_sldo_ctrl Register (offset = 428h) [reset = 0h]
768
9.3.7 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h]
769
9.3.8 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h]
770
9.3.9 bandgap_ctrl Register (offset = 448h) [reset = 0h]
771
9.3.10 bandgap_trim Register (offset = 44Ch) [reset = 0h]
772
9.3.11 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h]
773
9.3.12 mosc_ctrl Register (offset = 468h) [reset = 0h]
774
9.3.13 deepsleep_ctrl Register (offset = 470h) [reset = 0h]
775
9.3.14 dpll_pwr_sw_status (offset = 50Ch) [reset = 0h]
776
9.3.15 device_id Register (offset = 600h) [reset = 0x]
777
9.3.16 dev_feature Register (offset = 604h) [reset = 0h]
778
9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h]
779
9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h]
780
9.3.19 mmu_cfg Register (offset = 610h) [reset = 0h]
781
9.3.20 tptc_cfg Register (offset = 614h) [reset = 0h]
782
9.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h]
783
9.3.22 usb_sts0 Register (offset = 624h) [reset = 0h]
785
9.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h]
786
9.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h]
788
9.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h]
789
9.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h]
790
9.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h]
791
9.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h]
792
9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h]
793
9.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h]
794
9.3.31 gmii_sel Register (offset = 650h) [reset = 0h]
795
9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h]
796
9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h]
797
9.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h]
798
9.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h]
799
9.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h]
800
9.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h]
801
9.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h]
802
9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h]
803
9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h]
804
9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h]
805
9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h]
806
9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h]
807
9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h]
808
9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h]
809
9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h]
810
9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h]
811
9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h]
812
9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h]
813
9.3.50 efuse_sma Register (offset = 7FCh) [reset = 0h]
814
9.3.51 conf_<module>_<pin> Register (offset = 800h–A34h)
815
9.3.52 cqdetect_status Register (offset = E00h) [reset = 0h]
816
9.3.53 ddr_io_ctrl Register (offset = E04h) [reset = 0h]
817
9.3.54 vtp_ctrl Register (offset = E0Ch) [reset = 0h]
818
9.3.55 vref_ctrl Register (offset = E14h) [reset = 0h]
819
9.3.56 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h]
820
9.3.57 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h]
821
9.3.58 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h]
822
9.3.59 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h]
823
9.3.60 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h]
824
9.3.61 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h]
825
9.3.62 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h]
826
9.3.63 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h]
827
9.3.64 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h]
828
9.3.65 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h]
829
9.3.66 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h]
830
9.3.67 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h]
831
9.3.68 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h]
832
9.3.69 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h]
833
9.3.70 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h]
834
9.3.71 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h]
835
9.3.72 timer_evt_capt Register (offset = FD0h) [reset = 0h]
836
9.3.73 ecap_evt_capt Register (offset = FD4h) [reset = 0h]
837
9.3.74 adc_evt_capt Register (offset = FD8h) [reset = 0h]
838
9.3.75 reset_iso Register (offset = 1000h) [reset = 0h]
839
9.3.76 dpll_pwr_sw_ctrl Register (offset = 1318h) [reset = 0h]
840
9.3.77 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h]
842
9.3.78 sma2 Register (offset = 1320h) [reset = 0h]
843
9.3.79 m3_txev_eoi Register (offset = 1324h) [reset = 0h]
844
9.3.80 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h]
845
9.3.81 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h]
846
9.3.82 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h]
847
9.3.83 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h]
848
9.3.84 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h]
849
9.3.85 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h]
850
9.3.86 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h]
851
9.3.87 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h]
852
9.3.88 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h]
853
9.3.89 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h]
855
9.3.90 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h]
857
9.3.91 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h]
859
9.3.92 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h]
861
10 Interconnects
863
10.1 Introduction
864
10.1.1 Terminology
864
10.1.2 L3 Interconnect
864
10.1.2.1 L3 Topology
864
10.1.2.2 L3 Port Mapping
865
10.1.2.3 Interconnect Requirements
866
10.1.2.4 ConnID Assignment
867
10.1.3 L4 Interconnect
868
11 Enhanced Direct Memory Access (EDMA)
869
11.1 Introduction
870
11.1.1 EDMA3 Controller Block Diagram
870
11.1.2 Third-Party Channel Controller (TPCC) Overview
870
11.1.2.1 TPCC Features
870
11.1.2.2 Unsupported TPCC Features
871
11.1.3 Third-Party Transfer Controller (TPTC) Overview
871
11.1.3.1 TPTC Features
871
11.1.3.2 Unsupported TPTC Features
872
11.2 Integration
873
11.2.1 Third-Party Channel Controller (TPCC) Integration
873
11.2.1.1 TPCC Connectivity Attributes
873
11.2.1.2 TPCC Clock and Reset Management
873
11.2.1.3 TPCC Pin List
874
11.2.2 Third-Party Transfer Controller (TPTC) Integration
874
11.2.2.1 TPTC Connectivity Attributes
874
11.2.2.2 TPTC Clock and Reset Management
874
11.2.2.3 TPTC Pin List
875
11.3 Functional Description
876
11.3.1 Functional Overview
876
11.3.1.1 EDMA3 Channel Controller (EDMA3CC)
876
11.3.1.2 EDMA3 Transfer Controller (EDMA3TC)
878
11.3.2 Types of EDMA3 Transfers
879
11.3.2.1 A-Synchronized Transfers
880
11.3.2.2 AB-Synchronized Transfers
881
11.3.3 Parameter RAM (PaRAM)
881
11.3.3.1 PaRAM
882
11.3.3.2 EDMA3 Channel PaRAM Set Entry Fields
885
11.3.3.2.1 Channel Options Parameter (OPT)
885
11.3.3.2.2 Channel Source Address (SRC)
886
11.3.3.2.3 Channel Destination Address (DST)
886
11.3.3.2.4 Count for 1st Dimension (ACNT)
887
11.3.3.2.5 Count for 2nd Dimension (BCNT)
887
11.3.3.2.6 Count for 3rd Dimension (CCNT)
887
11.3.3.2.7 BCNT Reload (BCNTRLD)
887
11.3.3.2.8 Source B Index (SRCBIDX)
887
11.3.3.2.9 Destination B Index (DSTBIDX)
887
11.3.3.2.10 Source C Index (SRCCIDX)
888
11.3.3.2.11 Destination C Index (DSTCIDX)
888
11.3.3.2.12 Link Address (LINK)
888
11.3.3.3 Null PaRAM Set
888
11.3.3.4 Dummy PaRAM Set
888
11.3.3.5 Dummy Versus Null Transfer Comparison
889
11.3.3.6 Parameter Set Updates
889
11.3.3.7 Linking Transfers
891
11.3.3.8 Constant Addressing Mode Transfers/Alignment Issues
891
11.3.3.9 Element Size
892
11.3.4 Initiating a DMA Transfer
893
11.3.4.1 DMA Channel
894
11.3.4.1.1 Event-Triggered Transfer Request
894
11.3.4.1.2 Manually Triggered Transfer Request
894
11.3.4.1.3 Chain-Triggered Transfer Request
895
11.3.4.2 QDMA Channels
895
11.3.4.2.1 Auto-triggered and Link-Triggered Transfer Request
895
11.3.4.3 Comparison Between DMA and QDMA Channels
895
11.3.5 Completion of a DMA Transfer
896
11.3.5.1 Normal Completion
897
11.3.5.2 Early Completion
897
11.3.5.3 Dummy or Null Completion
897
11.3.6 Event, Channel, and PaRAM Mapping
897
11.3.6.1 DMA Channel to PaRAM Mapping
897
11.3.6.2 QDMA Channel to PaRAM Mapping
898
11.3.7 EDMA3 Channel Controller Regions
899
11.3.7.1 Region Overview
899
11.3.7.2 Channel Controller Regions
900
11.3.7.3 Region Interrupts
901
11.3.8 Chaining EDMA3 Channels
901
11.3.9 EDMA3 Interrupts
902
11.3.9.1 Transfer Completion Interrupts
902
11.3.9.1.1 Enabling Transfer Completion Interrupts
904
11.3.9.1.2 Clearing Transfer Completion Interrupts
905
11.3.9.2 EDMA3 Interrupt Servicing
905
11.3.9.3 Interrupt Evaluation Operations
906
11.3.9.4 Error Interrupts
907
11.3.10 Memory Protection
908
11.3.10.1 Active Memory Protection
908
11.3.10.2 Proxy Memory Protection
910
11.3.11 Event Queue(s)
912
11.3.11.1 DMA/QDMA Channel to Event Queue Mapping
912
11.3.11.2 Queue RAM Debug Visibility
913
11.3.11.3 Queue Resource Tracking
913
11.3.11.4 Performance Considerations
913
11.3.12 EDMA3 Transfer Controller (EDMA3TC)
914
11.3.12.1 Architecture Details
914
11.3.12.1.1 Command Fragmentation
914
11.3.12.1.2 TR Pipelining
914
11.3.12.1.3 Performance Tuning
915
11.3.12.2 Memory Protection
915
11.3.12.3 Error Generation
915
11.3.12.4 Debug Features
916
11.3.12.4.1 Destination FIFO Register Pointer
916
11.3.12.5 EDMA3TC Configuration
916
11.3.13 Event Dataflow
917
11.3.14 EDMA3 Prioritization
917
11.3.14.1 Channel Priority
917
11.3.14.2 Trigger Source Priority
918
11.3.14.3 Dequeue Priority
918
11.3.14.4 System (Transfer Controller) Priority
918
11.3.15 EDMA3 Operating Frequency (Clock Control)
918
11.3.16 Reset Considerations
918
11.3.17 Power Management
918
11.3.18 Emulation Considerations
918
11.3.19 EDMA Transfer Examples
920
11.3.19.1 Block Move Example
920
11.3.19.2 Subframe Extraction Example
921
11.3.19.3 Data Sorting Example
922
11.3.19.4 Peripheral Servicing Example
923
11.3.19.4.1 Non-bursting Peripherals
923
11.3.19.4.2 Bursting Peripherals
925
11.3.19.4.3 Continuous Operation
927
11.3.19.4.4 Ping-Pong Buffering
930
11.3.19.4.5 Transfer Chaining Examples
933
11.3.20 EDMA Events
936
11.4 EDMA3 Registers
939
11.4.1 EDMA3 Channel Controller Registers
939
11.4.1.1 Global Registers
942
11.4.1.1.1 Peripheral Identification Register (PID)
942
11.4.1.1.2 EDMA3CC Configuration Register (CCCFG)
943
11.4.1.1.3 EDMA3CC System Configuration Register (SYSCONFIG)
945
11.4.1.1.4 DMA Channel Map n Registers (DCHMAPn)
946
11.4.1.1.5 QDMA Channel Map n Registers (QCHMAPn)
947
11.4.1.1.6 DMA Channel Queue n Number Registers (DMAQNUMn)
948
11.4.1.1.7 QDMA Channel Queue Number Register (QDMAQNUM)
948
11.4.1.1.8 Queue Priority Register (QUEPRI)
950
11.4.1.2 Error Registers
951
11.4.1.2.1 Event Missed Registers (EMR/EMRH)
951
11.4.1.2.2 Event Missed Clear Registers (EMCR/EMCRH)
952
11.4.1.2.3 QDMA Event Missed Register (QEMR)
953
11.4.1.2.4 QDMA Event Missed Clear Register (QEMCR)
954
11.4.1.2.5 EDMA3CC Error Register (CCERR)
954
11.4.1.2.6 EDMA3CC Error Clear Register (CCERRCLR)
955
11.4.1.2.7 Error Evaluation Register (EEVAL)
957
11.4.1.3 Region Access Enable Registers
958
11.4.1.3.1 DMA Region Access Enable for Region m (DRAEm)
958
11.4.1.3.2 QDMA Region Access Enable Registers (QRAEm)
958
11.4.1.4 Status/Debug Visibility Registers
960
11.4.1.4.1 Event Queue Entry Registers (QxEy)
960
11.4.1.4.2 Queue Status Registers (QSTATn)
961
11.4.1.4.3 Queue Watermark Threshold A Register (QWMTHRA)
962
11.4.1.4.4 EDMA3CC Status Register (CCSTAT)
963
11.4.1.5 Memory Protection Address Space
965
11.4.1.5.1 Memory Protection Fault Address Register (MPFAR)
965
11.4.1.5.2 Memory Protection Fault Status Register (MPFSR)
966
11.4.1.5.3 Memory Protection Fault Command Register (MPFCR)
967
11.4.1.5.4 Memory Protection Page Attribute Register (MPPAn)
968
11.4.1.6 DMA Channel Registers
969
11.4.1.6.1 Event Registers (ER, ERH)
969
11.4.1.6.2 Event Clear Registers (ECR, ECRH)
971
11.4.1.6.3 Event Set Registers (ESR, ESRH)
972
11.4.1.6.4 Chained Event Registers (CER, CERH)
974
11.4.1.6.5 Event Enable Registers (EER, EERH)
976
11.4.1.6.6 Event Enable Clear Register (EECR, EECRH)
977
11.4.1.6.7 Event Enable Set Registers (EESR, EESRH)
978
11.4.1.6.8 Secondary Event Registers (SER, SERH)
979
11.4.1.6.9 Secondary Event Clear Registers (SECR, SECRH)
980
11.4.1.7 Interrupt Registers
981
11.4.1.7.1 Interrupt Enable Registers (IER, IERH)
981
11.4.1.7.2 Interrupt Enable Clear Register (IECR, IECRH)
981
11.4.1.7.3 Interrupt Enable Set Registers (IESR, IESRH)
983
11.4.1.7.4 Interrupt Pending Register (IPR, IPRH)
984
11.4.1.7.5 Interrupt Clear Registers (ICR, ICRH)
984
11.4.1.7.6 Interrupt Evaluate Register (IEVAL)
986
11.4.1.8 QDMA Registers
987
11.4.1.8.1 QDMA Event Register (QER)
987
11.4.1.8.2 QDMA Event Enable Register (QEER)
988
11.4.1.8.3 QDMA Event Enable Clear Register (QEECR)
989
11.4.1.8.4 QDMA Event Enable Set Register (QEESR)
990
11.4.1.8.5 QDMA Secondary Event Register (QSER)
991
11.4.1.8.6 QDMA Secondary Event Clear Register (QSECR)
992
11.4.2 EDMA3 Transfer Controller Registers
993
11.4.2.1 Peripheral Identification Register (PID)
994
11.4.2.2 EDMA3TC Configuration Register (TCCFG)
995
11.4.2.3 EDMA3TC System Configuration Register (SYSCONFIG)
996
11.4.2.4 EDMA3TC Channel Status Register (TCSTAT)
997
11.4.2.5 Error Registers
999
11.4.2.5.1 Error Register (ERRSTAT)
999
11.4.2.5.2 Error Enable Register (ERREN)
1000
11.4.2.5.3 Error Clear Register (ERRCLR)
1001
11.4.2.5.4 Error Details Register (ERRDET)
1002
11.4.2.5.5 Error Interrupt Command Register (ERRCMD)
1003
11.4.2.6 Read Rate Register (RDRATE)
1004
11.4.2.7 EDMA3TC Channel Registers
1005
11.4.2.7.1 Source Active Options Register (SAOPT)
1005
11.4.2.7.2 Source Active Source Address Register (SASRC)
1007
11.4.2.7.3 Source Active Count Register (SACNT)
1007
11.4.2.7.4 Source Active Destination Address Register (SADST)
1008
11.4.2.7.5 Source Active Source B-Dimension Index Register (SABIDX)
1008
11.4.2.7.6 Source Active Memory Protection Proxy Register (SAMPPRXY)
1009
11.4.2.7.7 Source Active Count Reload Register (SACNTRLD)
1010
11.4.2.7.8 Source Active Source Address B-Reference Register (SASRCBREF)
1010
11.4.2.7.9 Source Active Destination Address B-Reference Register (SADSTBREF)
1011
11.4.2.7.10 Destination FIFO Options Register (DFOPTn)
1012
11.4.2.7.11 Destination FIFO Source Address Register (DFSRCn)
1014
11.4.2.7.12 Destination FIFO Count Register (DFCNTn)
1014
11.4.2.7.13 Destination FIFO Destination Address Register (DFDSTn)
1015
11.4.2.7.14 Destination FIFO B-Index Register (DFBIDXn)
1015
11.4.2.7.15 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
1016
11.4.2.7.16 Destination FIFO Count Reload Register (DFCNTRLDn)
1017
11.4.2.7.17 Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
1017
11.4.2.7.18 Destination FIFO Destination Address B-Reference (DFDSTBREFn)
1018
11.5 Appendix A
1018
11.5.1 Debug Checklist
1018
11.5.2 Miscellaneous Programming/Debug Tips
1019
11.5.3 Setting Up a Transfer
1020
12 Touchscreen Controller
1022
12.1 Introduction
1023
12.1.1 TSC_ADC Features
1023
12.1.2 Unsupported TSC_ADC_SS Features
1023
12.2 Integration
1024
12.2.1 TSC_ADC Connectivity Attributes
1024
12.2.2 TSC_ADC Clock and Reset Management
1025
12.2.3 TSC_ADC Pin List
1025
12.3 Functional Description
1026
12.3.1 HW Synchronized or SW Channels
1026
12.3.2 Open Delay and Sample Delay
1026
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16)
1026
12.3.4 One-Shot (Single) or Continuous Mode
1026
12.3.5 Interrupts
1026
12.3.6 DMA Requests
1027
12.3.7 Analog Front End (AFE) Functional Block Diagram
1027
12.4 Operational Modes
1029
12.4.1 PenCtrl and PenIRQ
1030
12.5 Touchscreen Controller Registers
1033
12.5.1 TSC_ADC_SS Registers
1033
12.5.1.1 REVISION Register (offset = 0h) [reset = 47300001h]
1035
12.5.1.2 SYSCONFIG Register (offset = 10h) [reset = 0h]
1036
12.5.1.3 IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
1037
12.5.1.4 IRQSTATUS Register (offset = 28h) [reset = 0h]
1039
12.5.1.5 IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
1041
12.5.1.6 IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
1043
12.5.1.7 IRQWAKEUP Register (offset = 34h) [reset = 0h]
1045
12.5.1.8 DMAENABLE_SET Register (offset = 38h) [reset = 0h]
1046
12.5.1.9 DMAENABLE_CLR Register (offset = 3Ch) [reset = 0h]
1047
12.5.1.10 CTRL Register (offset = 40h) [reset = 0h]
1048
12.5.1.11 ADCSTAT Register (offset = 44h) [reset = 10h]
1049
12.5.1.12 ADCRANGE Register (offset = 48h) [reset = 0h]
1050
12.5.1.13 ADC_CLKDIV Register (offset = 4Ch) [reset = 0h]
1051
12.5.1.14 ADC_MISC Register (offset = 50h) [reset = 0h]
1052
12.5.1.15 STEPENABLE Register (offset = 54h) [reset = 0h]
1053
12.5.1.16 IDLECONFIG Register (offset = 58h) [reset = 0h]
1054
12.5.1.17 TS_CHARGE_STEPCONFIG Register (offset = 5Ch) [reset = 0h]
1055
12.5.1.18 TS_CHARGE_DELAY Register (offset = 60h) [reset = 1h]
1056
12.5.1.19 STEPCONFIG1 Register (offset = 64h) [reset = 0h]
1057
12.5.1.20 STEPDELAY1 Register (offset = 68h) [reset = 0h]
1058
12.5.1.21 STEPCONFIG2 Register (offset = 6Ch) [reset = 0h]
1059
12.5.1.22 STEPDELAY2 Register (offset = 70h) [reset = 0h]
1060
12.5.1.23 STEPCONFIG3 Register (offset = 74h) [reset = 0h]
1061
12.5.1.24 STEPDELAY3 Register (offset = 78h) [reset = 0h]
1062
12.5.1.25 STEPCONFIG4 Register (offset = 7Ch) [reset = 0h]
1063
12.5.1.26 STEPDELAY4 Register (offset = 80h) [reset = 0h]
1064
12.5.1.27 STEPCONFIG5 Register (offset = 84h) [reset = 0h]
1065
12.5.1.28 STEPDELAY5 Register (offset = 88h) [reset = 0h]
1066
12.5.1.29 STEPCONFIG6 Register (offset = 8Ch) [reset = 0h]
1067
12.5.1.30 STEPDELAY6 Register (offset = 90h) [reset = 0h]
1068
12.5.1.31 STEPCONFIG7 Register (offset = 94h) [reset = 0h]
1069
12.5.1.32 STEPDELAY7 Register (offset = 98h) [reset = 0h]
1070
12.5.1.33 STEPCONFIG8 Register (offset = 9Ch) [reset = 0h]
1071
12.5.1.34 STEPDELAY8 Register (offset = A0h) [reset = 0h]
1072
12.5.1.35 STEPCONFIG9 Register (offset = A4h) [reset = 0h]
1073
12.5.1.36 STEPDELAY9 Register (offset = A8h) [reset = 0h]
1074
12.5.1.37 STEPCONFIG10 Register (offset = ACh) [reset = 0h]
1075
12.5.1.38 STEPDELAY10 Register (offset = B0h) [reset = 0h]
1076
12.5.1.39 STEPCONFIG11 Register (offset = B4h) [reset = 0h]
1077
12.5.1.40 STEPDELAY11 Register (offset = B8h) [reset = 0h]
1078
12.5.1.41 STEPCONFIG12 Register (offset = BCh) [reset = 0h]
1079
12.5.1.42 STEPDELAY12 Register (offset = C0h) [reset = 0h]
1080
12.5.1.43 STEPCONFIG13 Register (offset = C4h) [reset = 0h]
1081
12.5.1.44 STEPDELAY13 Register (offset = C8h) [reset = 0h]
1082
12.5.1.45 STEPCONFIG14 Register (offset = CCh) [reset = 0h]
1083
12.5.1.46 STEPDELAY14 Register (offset = D0h) [reset = 0h]
1084
12.5.1.47 STEPCONFIG15 Register (offset = D4h) [reset = 0h]
1085
12.5.1.48 STEPDELAY15 Register (offset = D8h) [reset = 0h]
1086
12.5.1.49 STEPCONFIG16 Register (offset = DCh) [reset = 0h]
1087
12.5.1.50 STEPDELAY16 Register (offset = E0h) [reset = 0h]
1088
12.5.1.51 FIFO0COUNT Register (offset = E4h) [reset = 0h]
1089
12.5.1.52 FIFO0THRESHOLD Register (offset = E8h) [reset = 0h]
1090
12.5.1.53 DMA0REQ Register (offset = ECh) [reset = 0h]
1091
12.5.1.54 FIFO1COUNT Register (offset = F0h) [reset = 0h]
1092
12.5.1.55 FIFO1THRESHOLD Register (offset = F4h) [reset = 0h]
1093
12.5.1.56 DMA1REQ Register (offset = F8h) [reset = 0h]
1094
12.5.1.57 FIFO0DATA Register (offset = 100h) [reset = 0h]
1095
12.5.1.58 FIFO1DATA Register (offset = 200h) [reset = 0h]
1096
13 LCD Controller
1097
13.1 Introduction
1098
13.1.1 Purpose of the Peripheral
1098
13.1.2 Features
1099
13.2 Integration
1100
13.2.1 LCD Controller Connectivity Attributes
1100
13.2.2 LCD Controller Clock and Reset Management
1101
13.2.3 LCD Controller Pin List
1101
13.3 Functional Description
1102
13.3.1 Clocking
1102
13.3.1.1 Pixel Clock (LCD_PCLK)
1102
13.3.1.2 Horizontal Clock (LCD_HSYNC)
1103
13.3.1.3 Vertical Clock (LCD_VSYNC)
1103
13.3.1.4 LCD_AC_BIAS_EN
1103
13.3.2 LCD External I/O Signals
1104
13.3.3 DMA Engine
1105
13.3.3.1 Interrupts
1105
13.3.3.1.1 LIDD Mode
1105
13.3.3.1.2 Raster Mode
1105
13.3.3.1.3 Interrupt Handling
1106
13.3.4 LIDD Controller
1106
13.3.5 Raster Controller
1108
13.3.5.1 Logical Data Path
1109
13.3.5.2 Frame Buffer
1110
13.3.5.3 Palette
1114
13.3.5.4 Gray-Scaler/Serializer
1114
13.3.5.4.1 Passive (STN) Mode
1114
13.3.5.4.2 Active (TFT) Mode
1114
13.3.5.4.3 Summary of Color Depth
1115
13.3.5.5 Output Format
1116
13.3.5.5.1 Passive (STN) Mode
1116
13.3.5.5.2 Active (TFT) Mode
1116
13.3.5.6 Subpicture Feature
1117
13.3.6 Interrupt Conditions
1119
13.3.6.1 Highlander 0.8 Interrupts
1119
13.3.6.1.1 Highlander Interrupt Basics
1119
13.3.6.1.2 Raw Status Register
1119
13.3.6.1.3 Masked Status Register
1119
13.3.6.1.4 Interrupt Enable Set Register
1119
13.3.6.1.5 Interrupt Enable Clear Register
1119
13.3.6.1.6 End of Interrupt Register
1119
13.3.6.2 Interrupt Sources
1120
13.3.6.2.1 Overview of Interrupt Sources
1120
13.3.7 DMA
1121
13.3.8 Power Management
1121
13.4 Programming Model
1122
13.4.1 LCD Character Displays
1122
13.4.1.1 Configuration Registers, Setup, and Settings
1122
13.4.1.1.1 Configuration Registers
1122
13.4.1.1.2 Defining Panel Commands and Panel Data
1122
13.4.1.2 CPU Initiated Data Bus Transactions
1123
13.4.1.2.1 Initiating Data Bus Transactions
1123
13.4.1.3 DMA Initiated Data Bus Transactions for LIDD
1123
13.4.1.3.1 DMA Overview for MPU Bus Output
1123
13.4.1.3.2 MCU/LIDD DMA Setup: Example Pseudo Code
1124
13.4.1.4 Passive Matrix
1124
13.4.1.4.1 Monochrome Bitrate Awareness
1124
13.4.2 Active Matrix Displays
1125
13.4.2.1 Interfacing to Dual LVDS Transmitters
1125
13.4.3 System Interaction
1125
13.4.3.1 DMA End of Frame Interrupts
1125
13.4.4 Palette Lookup
1125
13.4.5 Test Logic
1127
13.4.6 Disable and Software Reset Sequence
1127
13.4.7 Precedence Order for Determining Frame Buffer Type
1128
13.5 LCD Registers
1128
13.5.1 PID Register (offset = 0h) [reset = 0h]
1130
13.5.2 CTRL Register (offset = 4h) [reset = 0h]
1131
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h]
1132
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h]
1133
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h]
1134
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h]
1135
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h]
1136
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h]
1137
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h]
1138
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h]
1139
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h]
1141
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h]
1142
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h]
1143
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h]
1145
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h]
1146
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h]
1147
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h]
1148
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h]
1149
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h]
1150
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h]
1151
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h]
1152
13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h]
1153
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h]
1155
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h]
1157
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h]
1159
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h]
1161
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h]
1162
14 Ethernet Subsystem
1163
14.1 Introduction
1164
14.1.1 Features
1164
14.1.2 Unsupported Features
1165
14.2 Integration
1166
14.2.1 Ethernet Switch Connectivity Attributes
1167
14.2.2 Ethernet Switch Clock and Reset Management
1168
14.2.3 Ethernet Switch Pin List
1169
14.2.4 Ethernet Switch RMII Clocking Details
1169
14.2.5 GMII Interface Signal Connections and Descriptions
1170
14.2.5.1 GMII Interface Signal Descriptions in GIG (1000Mbps) Mode
1171
14.2.5.2
1172
14.2.6 RMII Signal Connections and Descriptions
1173
14.2.7 RGMII Signal Connections and Descriptions
1174
14.3 Functional Description
1176
14.3.1 CPSW_3G Subsystem
1176
14.3.1.1 Interrupt Pacing
1176
14.3.1.2 Reset Isolation
1176
14.3.1.2.1 Modes of Operation
1177
14.3.1.3 Interrupts
1178
14.3.1.3.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
1178
14.3.1.3.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
1178
14.3.1.3.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
1179
14.3.1.3.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
1180
14.3.1.4 Embedded Memories
1181
14.3.2 CPSW_3G
1181
14.3.2.1 Media Independent Interface (GMII)
1182
14.3.2.2 IEEE 1588v2 Clock Synchronization Support
1182
14.3.2.2.1 IEEE 1588v2 Receive Packet Operation
1182
14.3.2.2.2 IEEE 1588v2 Transmit Packet Operation
1184
14.3.2.3 Device Level Ring (DLR) Support
1186
14.3.2.4 CPDMA RX and TX Interfaces
1186
14.3.2.4.1 CPPI Buffer Descriptors
1187
14.3.2.4.2 Receive DMA Interface
1192
14.3.2.4.3 Transmit DMA Interface
1193
14.3.2.4.4 Transmit Rate Limiting
1193
14.3.2.4.5 Command IDLE
1194
14.3.2.5 VLAN Aware Mode
1194
14.3.2.6 VLAN Unaware Mode
1194
14.3.2.7 Address Lookup Engine (ALE)
1194
14.3.2.7.1 Address Table Entry
1195
14.3.2.7.2 Packet Forwarding Processes
1200
14.3.2.7.3 Learning/Updating/Touching Processes
1203
14.3.2.8 Packet Priority Handling
1204
14.3.2.9 FIFO Memory Control
1204
14.3.2.10 FIFO Transmit Queue Control
1204
14.3.2.10.1 Normal Priority Mode
1205
14.3.2.10.2 Dual Mac Mode
1205
14.3.2.10.3 Rate Limit Mode
1205
14.3.2.11 Packet Padding
1206
14.3.2.12 Flow Control
1206
14.3.2.12.1 CPPI Port Flow Control
1206
14.3.2.12.2 Ethernet Port Flow Control
1207
14.3.2.13 Packet Drop Interface
1209
14.3.2.14 Short Gap
1209
14.3.2.15 Switch Latency
1209
14.3.2.16 Emulation Control
1210
14.3.2.17 Software IDLE
1210
14.3.2.18 Software Reset
1210
14.3.2.19 FIFO Loopback
1211
14.3.2.20 CPSW_3G Network Statistics
1211
14.3.2.20.1 Rx-only Statistics Descriptions
1211
14.3.2.20.2 Tx-only Statistics Descriptions
1215
14.3.2.20.3 Rx- and Tx-Shared Statistics Descriptions
1217
14.3.3 Ethernet Mac Sliver (CPGMAC_SL)
1223
14.3.3.1 GMII/MII Media Independent Interface
1223
14.3.3.1.1 Data Reception
1223
14.3.3.1.2 Data Transmission
1223
14.3.3.2 Frame Classification
1225
14.3.4 Command IDLE
1225
14.3.5 RMII Interface
1225
14.3.5.1 RMII Receive (RX)
1225
14.3.5.2 RMII Transmit (TX)
1226
14.3.6 RGMII Interface
1226
14.3.6.1 RGMII Receive (RX)
1226
14.3.6.2 In-Band Mode of Operation
1226
14.3.6.3 Forced Mode of Operation
1226
14.3.6.4 RGMII Transmit (TX)
1226
14.3.7 Common Platform Time Sync (CPTS)
1228
14.3.7.1 Architecture
1228
14.3.7.2 Time Sync Overview
1228
14.3.7.2.1 Time Sync Initialization
1228
14.3.7.2.2 Time Stamp Value
1229
14.3.7.2.3 Event FIFO
1229
14.3.7.2.4 Time Sync Events
1229
14.3.7.3 Interrupt Handling
1232
14.3.8 MDIO
1233
14.3.8.1 MII Management Interface Frame Formats
1233
14.3.8.2 Functional Description
1234
14.4 Software Operation
1235
14.4.1 Transmit Operation
1235
14.4.2 Receive Operation
1237
14.4.3 Initializing the MDIO Module
1238
14.4.4 Writing Data to a PHY Register
1238
14.4.5 Reading Data from a PHY Register
1239
14.4.6 Initialization and Configuration of CPSW
1239
14.5 Ethernet Subsystem Registers
1240
14.5.1 CPSW_ALE Registers
1240
14.5.1.1 IDVER Register (offset = 0h) [reset = 290104h]
1241
14.5.1.2 CONTROL Register (offset = 8h) [reset = 0h]
1242
14.5.1.3 PRESCALE Register (offset = 10h) [reset = 0h]
1244
14.5.1.4 UNKNOWN_VLAN Register (offset = 18h) [reset = 0h]
1245
14.5.1.5 TBLCTL Register (offset = 20h) [reset = 0h]
1246
14.5.1.6 TBLW2 Register (offset = 34h) [reset = 0h]
1247
14.5.1.7 TBLW1 Register (offset = 38h) [reset = 0h]
1248
14.5.1.8 TBLW0 Register (offset = 3Ch) [reset = 0h]
1249
14.5.1.9 PORTCTL0 Register (offset = 40h) [reset = 0h]
1250
14.5.1.10 PORTCTL1 Register (offset = 44h) [reset = 0h]
1251
14.5.1.11 PORTCTL2 Register (offset = 48h) [reset = 0h]
1252
14.5.1.12 PORTCTL3 Register (offset = 4Ch) [reset = 0h]
1253
14.5.1.13 PORTCTL4 Register (offset = 50h) [reset = 0h]
1254
14.5.1.14 PORTCTL5 Register (offset = 54h) [reset = 0h]
1255
14.5.2 CPSW_CPDMA Registers
1255
14.5.2.1 TX_IDVER Register (offset = 0h) [reset = 180108h]
1258
14.5.2.2 TX_CONTROL Register (offset = 4h) [reset = 0h]
1259
14.5.2.3 TX_TEARDOWN Register (offset = 8h) [reset = 0h]
1260
14.5.2.4 RX_IDVER Register (offset = 10h) [reset = C0107h]
1261
14.5.2.5 RX_CONTROL Register (offset = 14h) [reset = 0h]
1262
14.5.2.6 RX_TEARDOWN Register (offset = 18h) [reset = 0h]
1263
14.5.2.7 CPDMA_SOFT_RESET Register (offset = 1Ch) [reset = 0h]
1264
14.5.2.8 DMACONTROL Register (offset = 20h) [reset = 0h]
1265
14.5.2.9 DMASTATUS Register (offset = 24h) [reset = 0h]
1267
14.5.2.10 RX_BUFFER_OFFSET Register (offset = 28h) [reset = 0h]
1269
14.5.2.11 EMCONTROL Register (offset = 2Ch) [reset = 0h]
1270
14.5.2.12 TX_PRI0_RATE Register (offset = 30h) [reset = 0h]
1271
14.5.2.13 TX_PRI1_RATE Register (offset = 34h) [reset = 0h]
1272
14.5.2.14 TX_PRI2_RATE Register (offset = 38h) [reset = 0h]
1273
14.5.2.15 TX_PRI3_RATE Register (offset = 3Ch) [reset = 0h]
1274
14.5.2.16 TX_PRI4_RATE Register (offset = 40h) [reset = 0h]
1275
14.5.2.17 TX_PRI5_RATE Register (offset = 44h) [reset = 0h]
1276
14.5.2.18 TX_PRI6_RATE Register (offset = 48h) [reset = 0h]
1277
14.5.2.19 TX_PRI7_RATE Register (offset = 4Ch) [reset = 0h]
1278
14.5.2.20 TX_INTSTAT_RAW Register (offset = 80h) [reset = 0h]
1279
14.5.2.21 TX_INTSTAT_MASKED Register (offset = 84h) [reset = 0h]
1280
14.5.2.22 TX_INTMASK_SET Register (offset = 88h) [reset = 0h]
1281
14.5.2.23 TX_INTMASK_CLEAR Register (offset = 8Ch) [reset = 0h]
1282
14.5.2.24 CPDMA_IN_VECTOR Register (offset = 90h) [reset = 0h]
1283
14.5.2.25 CPDMA_EOI_VECTOR Register (offset = 94h) [reset = 0h]
1284
14.5.2.26 RX_INTSTAT_RAW Register (offset = A0h) [reset = 0h]
1285
14.5.2.27 RX_INTSTAT_MASKED Register (offset = A4h) [reset = 0h]
1286
14.5.2.28 RX_INTMASK_SET Register (offset = A8h) [reset = 0h]
1287
14.5.2.29 RX_INTMASK_CLEAR Register (offset = ACh) [reset = 0h]
1288
14.5.2.30 DMA_INTSTAT_RAW Register (offset = B0h) [reset = 0h]
1289
14.5.2.31 DMA_INTSTAT_MASKED Register (offset = B4h) [reset = 0h]
1290
14.5.2.32 DMA_INTMASK_SET Register (offset = B8h) [reset = 0h]
1291
14.5.2.33 DMA_INTMASK_CLEAR Register (offset = BCh) [reset = 0h]
1292
14.5.2.34 RX0_PENDTHRESH Register (offset = C0h) [reset = 0h]
1293
14.5.2.35 RX1_PENDTHRESH Register (offset = C4h) [reset = 0h]
1294
14.5.2.36 RX2_PENDTHRESH Register (offset = C8h) [reset = 0h]
1295
14.5.2.37 RX3_PENDTHRESH Register (offset = CCh) [reset = 0h]
1296
14.5.2.38 RX4_PENDTHRESH Register (offset = D0h) [reset = 0h]
1297
14.5.2.39 RX5_PENDTHRESH Register (offset = D4h) [reset = 0h]
1298
14.5.2.40 RX6_PENDTHRESH Register (offset = D8h) [reset = 0h]
1299
14.5.2.41 RX7_PENDTHRESH Register (offset = DCh) [reset = 0h]
1300
14.5.2.42 RX0_FREEBUFFER Register (offset = E0h) [reset = 0h]
1301
14.5.2.43 RX1_FREEBUFFER Register (offset = E4h) [reset = 0h]
1302
14.5.2.44 RX2_FREEBUFFER Register (offset = E8h) [reset = 0h]
1303
14.5.2.45 RX3_FREEBUFFER Register (offset = ECh) [reset = 0h]
1304
14.5.2.46 RX4_FREEBUFFER Register (offset = F0h) [reset = 0h]
1305
14.5.2.47 RX5_FREEBUFFER Register (offset = F4h) [reset = 0h]
1306
14.5.2.48 RX6_FREEBUFFER Register (offset = F8h) [reset = 0h]
1307
14.5.2.49 RX7_FREEBUFFER Register (offset = FCh) [reset = 0h]
1308
14.5.3 CPSW_CPTS Registers
1308
14.5.3.1 CPTS_IDVER Register (offset = 0h) [reset = 4E8A0101h]
1310
14.5.3.2 CPTS_CONTROL Register (offset = 4h) [reset = 0h]
1311
14.5.3.3 CPTS_TS_PUSH Register (offset = Ch) [reset = 0h]
1312
14.5.3.4 CPTS_TS_LOAD_VAL Register (offset = 10h) [reset = 0h]
1313
14.5.3.5 CPTS_TS_LOAD_EN Register (offset = 14h) [reset = 0h]
1314
14.5.3.6 CPTS_INTSTAT_RAW Register (offset = 20h) [reset = 0h]
1315
14.5.3.7 CPTS_INTSTAT_MASKED Register (offset = 24h) [reset = 0h]
1316
14.5.3.8 CPTS_INT_ENABLE Register (offset = 28h) [reset = 0h]
1317
14.5.3.9 CPTS_EVENT_POP Register (offset = 30h) [reset = 0h]
1318
14.5.3.10 CPTS_EVENT_LOW Register (offset = 34h) [reset = 0h]
1319
14.5.3.11 CPTS_EVENT_HIGH Register (offset = 38h) [reset = 0h]
1320
14.5.4 CPSW_STATS Registers
1321
14.5.5 CPDMA_STATERAM Registers
1321
14.5.5.1 TX0_HDP Register (offset = A00h) [reset = 0h]
1324
14.5.5.2 TX1_HDP Register (offset = A04h) [reset = 0h]
1325
14.5.5.3 TX2_HDP Register (offset = A08h) [reset = 0h]
1326
14.5.5.4 TX3_HDP Register (offset = A0Ch) [reset = 0h]
1327
14.5.5.5 TX4_HDP Register (offset = A10h) [reset = 0h]
1328
14.5.5.6 TX5_HDP Register (offset = A14h) [reset = 0h]
1329
14.5.5.7 TX6_HDP Register (offset = A18h) [reset = 0h]
1330
14.5.5.8 TX7_HDP Register (offset = A1Ch) [reset = 0h]
1331
14.5.5.9 RX0_HDP Register (offset = A20h) [reset = 0h]
1332
14.5.5.10 RX1_HDP Register (offset = A24h) [reset = 0h]
1333
14.5.5.11 RX2_HDP Register (offset = A28h) [reset = 0h]
1334
14.5.5.12 RX3_HDP Register (offset = A2Ch) [reset = 0h]
1335
14.5.5.13 RX4_HDP Register (offset = A30h) [reset = 0h]
1336
14.5.5.14 RX5_HDP Register (offset = A34h) [reset = 0h]
1337
14.5.5.15 RX6_HDP Register (offset = A38h) [reset = 0h]
1338
14.5.5.16 RX7_HDP Register (offset = A3Ch) [reset = 0h]
1339
14.5.5.17 TX0_CP Register (offset = A40h) [reset = 0h]
1340
14.5.5.18 TX1_CP Register (offset = A44h) [reset = 0h]
1341
14.5.5.19 TX2_CP Register (offset = A48h) [reset = 0h]
1342
14.5.5.20 TX3_CP Register (offset = A4Ch) [reset = 0h]
1343
14.5.5.21 TX4_CP Register (offset = A50h) [reset = 0h]
1344
14.5.5.22 TX5_CP Register (offset = A54h) [reset = 0h]
1345
14.5.5.23 TX6_CP Register (offset = A58h) [reset = 0h]
1346
14.5.5.24 TX7_CP Register (offset = A5Ch) [reset = 0h]
1347
14.5.5.25 RX0_CP Register (offset = A60h) [reset = 0h]
1348
14.5.5.26 RX1_CP Register (offset = A64h) [reset = 0h]
1349
14.5.5.27 RX2_CP Register (offset = A68h) [reset = 0h]
1350
14.5.5.28 RX3_CP Register (offset = A6Ch) [reset = 0h]
1351
14.5.5.29 RX4_CP Register (offset = A70h) [reset = 0h]
1352
14.5.5.30 RX5_CP Register (offset = A74h) [reset = 0h]
1353
14.5.5.31 RX6_CP Register (offset = A78h) [reset = 0h]
1354
14.5.5.32 RX7_CP Register (offset = A7Ch) [reset = 0h]
1355
14.5.6 CPSW_PORT Registers
1355
14.5.6.1 P0_CONTROL Register (offset = 0h) [reset = 0h]
1357
14.5.6.2 P0_MAX_BLKS Register (offset = 8h) [reset = 104h]
1358
14.5.6.3 P0_BLK_CNT Register (offset = Ch) [reset = 41h]
1359
14.5.6.4 P0_TX_IN_CTL Register (offset = 10h) [reset = 40C0h]
1360
14.5.6.5 P0_PORT_VLAN Register (offset = 14h) [reset = 0h]
1361
14.5.6.6 P0_TX_PRI_MAP Register (offset = 18h) [reset = 33221001h]
1362
14.5.6.7 P0_CPDMA_TX_PRI_MAP Register (offset = 1Ch) [reset = 76543210h]
1363
14.5.6.8 P0_CPDMA_RX_CH_MAP Register (offset = 20h) [reset = 0h]
1364
14.5.6.9 P0_RX_DSCP_PRI_MAP0 Register (offset = 30h) [reset = 0h]
1365
14.5.6.10 P0_RX_DSCP_PRI_MAP1 Register (offset = 34h) [reset = 0h]
1366
14.5.6.11 P0_RX_DSCP_PRI_MAP2 Register (offset = 38h) [reset = 0h]
1367
14.5.6.12 P0_RX_DSCP_PRI_MAP3 Register (offset = 3Ch) [reset = 0h]
1368
14.5.6.13 P0_RX_DSCP_PRI_MAP4 Register (offset = 40h) [reset = 0h]
1369
14.5.6.14 P0_RX_DSCP_PRI_MAP5 Register (offset = 44h) [reset = 0h]
1370
14.5.6.15 P0_RX_DSCP_PRI_MAP6 Register (offset = 48h) [reset = 0h]
1371
14.5.6.16 P0_RX_DSCP_PRI_MAP7 Register (offset = 4Ch) [reset = 0h]
1372
14.5.6.17 P1_CONTROL Register (offset = 100h) [reset = 0h]
1373
14.5.6.18 P1_MAX_BLKS Register (offset = 108h) [reset = 113h]
1375
14.5.6.19 P1_BLK_CNT Register (offset = 10Ch) [reset = 41h]
1376
14.5.6.20 P1_TX_IN_CTL Register (offset = 110h) [reset = 80040C0h]
1377
14.5.6.21 P1_PORT_VLAN Register (offset = 114h) [reset = 0h]
1378
14.5.6.22 P1_TX_PRI_MAP Register (offset = 118h) [reset = 33221001h]
1379
14.5.6.23 P1_TS_SEQ_MTYPE Register (offset = 11Ch) [reset = 1E0000h]
1380
14.5.6.24 P1_SA_LO Register (offset = 120h) [reset = 0h]
1381
14.5.6.25 P1_SA_HI Register (offset = 124h) [reset = 0h]
1382
14.5.6.26 P1_SEND_PERCENT Register (offset = 128h) [reset = 0h]
1383
14.5.6.27 P1_RX_DSCP_PRI_MAP0 Register (offset = 130h) [reset = 0h]
1384
14.5.6.28 P1_RX_DSCP_PRI_MAP1 Register (offset = 134h) [reset = 0h]
1385
14.5.6.29 P1_RX_DSCP_PRI_MAP2 Register (offset = 138h) [reset = 0h]
1386
14.5.6.30 P1_RX_DSCP_PRI_MAP3 Register (offset = 13Ch) [reset = 0h]
1387
14.5.6.31 P1_RX_DSCP_PRI_MAP4 Register (offset = 140h) [reset = 0h]
1388
14.5.6.32 P1_RX_DSCP_PRI_MAP5 Register (offset = 144h) [reset = 0h]
1389
14.5.6.33 P1_RX_DSCP_PRI_MAP6 Register (offset = 148h) [reset = 0h]
1390
14.5.6.34 P1_RX_DSCP_PRI_MAP7 Register (offset = 14Ch) [reset = 0h]
1391
14.5.6.35 P2_CONTROL Register (offset = 200h) [reset = 0h]
1392
14.5.6.36 P2_MAX_BLKS Register (offset = 208h) [reset = 113h]
1394
14.5.6.37 P2_BLK_CNT Register (offset = 20Ch) [reset = 41h]
1395
14.5.6.38 P2_TX_IN_CTL Register (offset = 210h) [reset = 80040C0h]
1396
14.5.6.39 P2_PORT_VLAN Register (offset = 214h) [reset = 0h]
1397
14.5.6.40 P2_TX_PRI_MAP Register (offset = 218h) [reset = 33221001h]
1398
14.5.6.41 P2_TS_SEQ_MTYPE Register (offset = 21Ch) [reset = 1E0000h]
1399
14.5.6.42 P2_SA_LO Register (offset = 220h) [reset = 0h]
1400
14.5.6.43 P2_SA_HI Register (offset = 224h) [reset = 0h]
1401
14.5.6.44 P2_SEND_PERCENT Register (offset = 228h) [reset = 0h]
1402
14.5.6.45 P2_RX_DSCP_PRI_MAP0 Register (offset = 230h) [reset = 0h]
1403
14.5.6.46 P2_RX_DSCP_PRI_MAP1 Register (offset = 234h) [reset = 0h]
1404
14.5.6.47 P2_RX_DSCP_PRI_MAP2 Register (offset = 238h) [reset = 0h]
1405
14.5.6.48 P2_RX_DSCP_PRI_MAP3 Register (offset = 23Ch) [reset = 0h]
1406
14.5.6.49 P2_RX_DSCP_PRI_MAP4 Register (offset = 240h) [reset = 0h]
1407
14.5.6.50 P2_RX_DSCP_PRI_MAP5 Register (offset = 244h) [reset = 0h]
1408
14.5.6.51 P2_RX_DSCP_PRI_MAP6 Register (offset = 248h) [reset = 0h]
1409
14.5.6.52 P2_RX_DSCP_PRI_MAP7 Register (offset = 24Ch) [reset = 0h]
1410
14.5.7 CPSW_SL Registers
1410
14.5.7.1 IDVER Register (offset = 0h) [reset = 170112h]
1412
14.5.7.2 MACCONTROL Register (offset = 4h) [reset = 0h]
1413
14.5.7.3 MACSTATUS Register (offset = 8h) [reset = 0h]
1416
14.5.7.4 SOFT_RESET Register (offset = Ch) [reset = 0h]
1417
14.5.7.5 RX_MAXLEN Register (offset = 10h) [reset = 5EEh]
1418
14.5.7.6 BOFFTEST Register (offset = 14h) [reset = 0h]
1419
14.5.7.7 RX_PAUSE Register (offset = 18h) [reset = 0h]
1420
14.5.7.8 TX_PAUSE Register (offset = 1Ch) [reset = 0h]
1421
14.5.7.9 EMCONTROL Register (offset = 20h) [reset = 0h]
1422
14.5.7.10 RX_PRI_MAP Register (offset = 24h) [reset = 76543210h]
1423
14.5.7.11 TX_GAP Register (offset = 28h) [reset = Ch]
1424
14.5.8 CPSW_SS Registers
1424
14.5.8.1 ID_VER Register (offset = 0h) [reset = 190112h]
1425
14.5.8.2 CONTROL Register (offset = 4h) [reset = 0h]
1426
14.5.8.3 SOFT_RESET Register (offset = 8h) [reset = 0h]
1427
14.5.8.4 STAT_PORT_EN Register (offset = Ch) [reset = 0h]
1428
14.5.8.5 PTYPE Register (offset = 10h) [reset = 0h]
1429
14.5.8.6 SOFT_IDLE Register (offset = 14h) [reset = 0h]
1430
14.5.8.7 THRU_RATE Register (offset = 18h) [reset = 3003h]
1431
14.5.8.8 GAP_THRESH Register (offset = 1Ch) [reset = Bh]
1432
14.5.8.9 TX_START_WDS Register (offset = 20h) [reset = 20h]
1433
14.5.8.10 FLOW_CONTROL Register (offset = 24h) [reset = 1h]
1434
14.5.8.11 VLAN_LTYPE Register (offset = 28h) [reset = 81008100h]
1435
14.5.8.12 TS_LTYPE Register (offset = 2Ch) [reset = 0h]
1436
14.5.8.13 DLR_LTYPE Register (offset = 30h) [reset = 80E1h]
1437
14.5.9 CPSW_WR Registers
1437
14.5.9.1 IDVER Register (offset = 0h) [reset = 4EDB0100h]
1439
14.5.9.2 SOFT_RESET Register (offset = 4h) [reset = 0h]
1440
14.5.9.3 CONTROL Register (offset = 8h) [reset = 0h]
1441
14.5.9.4 INT_CONTROL Register (offset = Ch) [reset = 0h]
1442
14.5.9.5 C0_RX_THRESH_EN Register (offset = 10h) [reset = 0h]
1443
14.5.9.6 C0_RX_EN Register (offset = 14h) [reset = 0h]
1444
14.5.9.7 C0_TX_EN Register (offset = 18h) [reset = 0h]
1445
14.5.9.8 C0_MISC_EN Register (offset = 1Ch) [reset = 0h]
1446
14.5.9.9 C1_RX_THRESH_EN Register (offset = 20h) [reset = 0h]
1447
14.5.9.10 C1_RX_EN Register (offset = 24h) [reset = 0h]
1448
14.5.9.11 C1_TX_EN Register (offset = 28h) [reset = 0h]
1449
14.5.9.12 C1_MISC_EN Register (offset = 2Ch) [reset = 0h]
1450
14.5.9.13 C2_RX_THRESH_EN Register (offset = 30h) [reset = 0h]
1451
14.5.9.14 C2_RX_EN Register (offset = 34h) [reset = 0h]
1452
14.5.9.15 C2_TX_EN Register (offset = 38h) [reset = 0h]
1453
14.5.9.16 C2_MISC_EN Register (offset = 3Ch) [reset = 0h]
1454
14.5.9.17 C0_RX_THRESH_STAT Register (offset = 40h) [reset = 0h]
1455
14.5.9.18 C0_RX_STAT Register (offset = 44h) [reset = 0h]
1456
14.5.9.19 C0_TX_STAT Register (offset = 48h) [reset = 0h]
1457
14.5.9.20 C0_MISC_STAT Register (offset = 4Ch) [reset = 0h]
1458
14.5.9.21 C1_RX_THRESH_STAT Register (offset = 50h) [reset = 0h]
1459
14.5.9.22 C1_RX_STAT Register (offset = 54h) [reset = 0h]
1460
14.5.9.23 C1_TX_STAT Register (offset = 58h) [reset = 0h]
1461
14.5.9.24 C1_MISC_STAT Register (offset = 5Ch) [reset = 0h]
1462
14.5.9.25 C2_RX_THRESH_STAT Register (offset = 60h) [reset = 0h]
1463
14.5.9.26 C2_RX_STAT Register (offset = 64h) [reset = 0h]
1464
14.5.9.27 C2_TX_STAT Register (offset = 68h) [reset = 0h]
1465
14.5.9.28 C2_MISC_STAT Register (offset = 6Ch) [reset = 0h]
1466
14.5.9.29 C0_RX_IMAX Register (offset = 70h) [reset = 0h]
1467
14.5.9.30 C0_TX_IMAX Register (offset = 74h) [reset = 0h]
1468
14.5.9.31 C1_RX_IMAX Register (offset = 78h) [reset = 0h]
1469
14.5.9.32 C1_TX_IMAX Register (offset = 7Ch) [reset = 0h]
1470
14.5.9.33 C2_RX_IMAX Register (offset = 80h) [reset = 0h]
1471
14.5.9.34 C2_TX_IMAX Register (offset = 84h) [reset = 0h]
1472
14.5.9.35 RGMII_CTL Register (offset = 88h) [reset = 0h]
1473
14.5.10 Management Data Input/Output (MDIO) Registers
1473
14.5.10.1 MDIO Version Register (MDIOVER)
1474
14.5.10.2 MDIO Control Register (MDIOCONTROL)
1475
14.5.10.3 PHY Acknowledge Status Register (MDIOALIVE)
1475
14.5.10.4 PHY Link Status Register (MDIOLINK)
1476
14.5.10.5 MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW)
1477
14.5.10.6 MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED)
1477
14.5.10.7 MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW)
1478
14.5.10.8 MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED)
1478
14.5.10.9 MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET)
1479
14.5.10.10 MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR)
1480
14.5.10.11 MDIO User Access Register 0 (MDIOUSERACCESS0)
1481
14.5.10.12 MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0)
1482
14.5.10.13 MDIO User Access Register 1 (MDIOUSERACCESS1)
1483
14.5.10.14 MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1)
1484
15 Pulse-Width Modulation Subsystem (PWMSS)
1485
15.1 Pulse-Width Modulation Subsystem (PWMSS)
1486
15.1.1 Introduction
1486
15.1.1.1 Features
1486
15.1.1.2 Unsupported Features
1487
15.1.2 Integration
1488
15.1.2.1 PWMSS Connectivity Attributes
1488
15.1.2.2 PWMSS Clock and Reset Management
1489
15.1.2.3 PWMSS Pin list
1489
15.1.3 PWMSS Registers
1489
15.1.3.1 IDVER Register (offset = 0h) [reset = 40000000h]
1490
15.1.3.2 SYSCONFIG Register (offset = 4h) [reset = 28h]
1491
15.1.3.3 CLKCONFIG Register (offset = 8h) [reset = 111h]
1492
15.1.3.4 CLKSTATUS Register (offset = Ch) [reset = 0h]
1493
15.2 Enhanced PWM (ePWM) Module
1494
15.2.1 Introduction
1494
15.2.1.1 Submodule Overview
1494
15.2.2 Functional Description
1498
15.2.2.1 Overview
1498
15.2.2.2 Proper Interrupt Initialization Procedure
1501
15.2.2.3 Time-Base (TB) Submodule
1501
15.2.2.3.1 Purpose of the Time-Base Submodule
1502
15.2.2.3.2 Controlling and Monitoring the Time-Base Submodule
1503
15.2.2.3.3 Calculating PWM Period and Frequency
1504
15.2.2.3.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
1507
15.2.2.3.5 Time-Base Counter Modes and Timing Waveforms
1507
15.2.2.4 Counter-Compare (CC) Submodule
1511
15.2.2.4.1 Purpose of the Counter-Compare Submodule
1512
15.2.2.4.2 Controlling and Monitoring the Counter-Compare Submodule
1512
15.2.2.4.3 Operational Highlights for the Counter-Compare Submodule
1513
15.2.2.4.4 Count Mode Timing Waveforms
1513
15.2.2.5 Action-Qualifier (AQ) Submodule
1516
15.2.2.5.1 Purpose of the Action-Qualifier Submodule
1516
15.2.2.5.2 Controlling and Monitoring the Action-Qualifier Submodule
1516
15.2.2.5.3 Action-Qualifier Event Priority
1519
15.2.2.5.4 Waveforms for Common Configurations
1520
15.2.2.6 Dead-Band Generator (DB) Submodule
1534
15.2.2.6.1 Purpose of the Dead-Band Submodule
1534
15.2.2.6.2 Controlling and Monitoring the Dead-Band Submodule
1534
15.2.2.6.3 Operational Highlights for the Dead-Band Generator Submodule
1535
15.2.2.7 PWM-Chopper (PC) Submodule
1538
15.2.2.7.1 Purpose of the PWM-Chopper Submodule
1538
15.2.2.7.2 Controlling the PWM-Chopper Submodule
1538
15.2.2.7.3 Operational Highlights for the PWM-Chopper Submodule
1539
15.2.2.7.4 Waveforms
1540
15.2.2.8 Trip-Zone (TZ) Submodule
1542
15.2.2.8.1 Purpose of the Trip-Zone Submodule
1542
15.2.2.8.2 Controlling and Monitoring the Trip-Zone Submodule
1543
15.2.2.8.3 Operational Highlights for the Trip-Zone Submodule
1543
15.2.2.8.4 Generating Trip Event Interrupts
1544
15.2.2.9 Event-Trigger (ET) Submodule
1546
15.2.2.9.1 Purpose of the Event-Trigger Submodule
1546
15.2.2.9.2 Controlling and Monitoring the Event-Trigger Submodule
1546
15.2.2.9.3 Operational Overview of the Event-Trigger Submodule
1547
15.2.2.10 High-Resolution PWM (HRPWM) Submodule
1550
15.2.2.10.1 Purpose of the High-Resolution PWM Submodule
1551
15.2.2.10.2 Architecture of the High-Resolution PWM Submodule
1552
15.2.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule
1552
15.2.2.10.4 Configuring the High-Resolution PWM Submodule
1553
15.2.2.10.5 Operational Highlights for the High-Resolution PWM Submodule
1553
15.2.3 Use Cases
1557
15.2.3.1 Overview of Multiple Modules
1557
15.2.3.2 Key Configuration Capabilities
1558
15.2.3.3 Controlling Multiple Buck Converters With Independent Frequencies
1559
15.2.3.4 Controlling Multiple Buck Converters With Same Frequencies
1562
15.2.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
1565
15.2.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
1568
15.2.3.7 Practical Applications Using Phase Control Between PWM Modules
1572
15.2.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
1573
15.2.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
1578
15.2.4 Registers
1581
15.2.4.1 Time-Base Submodule Registers
1582
15.2.4.1.1 Time-Base Control Register (TBCTL)
1582
15.2.4.1.2 Time-Base Status Register (TBSTS)
1584
15.2.4.1.3 Time-Base Phase Register (TBPHS)
1584
15.2.4.1.4 Time-Base Counter Register (TBCNT)
1585
15.2.4.1.5 Time-Base Period Register (TBPRD)
1586
15.2.4.2 Counter-Compare Submodule Registers
1586
15.2.4.2.1 Counter-Compare Control Register (CMPCTL)
1587
15.2.4.2.2 Counter-Compare A Register (CMPA)
1588
15.2.4.2.3 Counter-Compare B Register (CMPB)
1589
15.2.4.3 Action-Qualifier Submodule Registers
1589
15.2.4.3.1 Action-Qualifier Output A Control Register (AQCTLA)
1590
15.2.4.3.2 Action-Qualifier Output B Control Register (AQCTLB)
1591
15.2.4.3.3 Action-Qualifier Software Force Register (AQSFRC)
1592
15.2.4.3.4 Action-Qualifier Continuous Software Force Register (AQCSFRC)
1593
15.2.4.4 Dead-Band Generator Submodule Registers
1593
15.2.4.4.1 Dead-Band Generator Control Register (DBCTL)
1594
15.2.4.4.2 Dead-Band Generator Rising Edge Delay Register (DBRED)
1595
15.2.4.4.3 Dead-Band Generator Falling Edge Delay Register (DBFED)
1595
15.2.4.5 Trip-Zone Submodule Registers
1596
15.2.4.5.1 Trip-Zone Select Register (TZSEL)
1596
15.2.4.5.2 Trip-Zone Control Register (TZCTL)
1597
15.2.4.5.3 Trip-Zone Enable Interrupt Register (TZEINT)
1597
15.2.4.5.4 Trip-Zone Flag Register (TZFLG)
1598
15.2.4.5.5 Trip-Zone Clear Register (TZCLR)
1599
15.2.4.5.6 Trip-Zone Force Register (TZFRC)
1599
15.2.4.6 Event-Trigger Submodule Registers
1600
15.2.4.6.1 Event-Trigger Selection Register (ETSEL)
1600
15.2.4.6.2 Event-Trigger Prescale Register (ETPS)
1601
15.2.4.6.3 Event-Trigger Flag Register (ETFLG)
1602
15.2.4.6.4 Event-Trigger Clear Register (ETCLR)
1602
15.2.4.6.5 Event-Trigger Force Register (ETFRC)
1603
15.2.4.7 PWM-Chopper Submodule Register
1604
15.2.4.8 High-Resolution PWM Submodule Registers
1604
15.2.4.8.1 Time-Base Phase High-Resolution Register (TBPHSHR)
1605
15.2.4.8.2 Counter-Compare A High-Resolution Register (CMPAHR)
1605
15.2.4.8.3 HRPWM Control Register (HRCTL)
1606
15.3 Enhanced Capture (eCAP) Module
1607
15.3.1 Introduction
1607
15.3.1.1 Purpose of the Peripheral
1607
15.3.1.2 Features
1607
15.3.2 Functional Description
1608
15.3.2.1 Capture and APWM Operating Mode
1609
15.3.2.2 Capture Mode Description
1610
15.3.2.2.1 Event Prescaler
1611
15.3.2.2.2 Edge Polarity Select and Qualifier
1612
15.3.2.2.3 Continuous/One-Shot Control
1612
15.3.2.2.4 32-Bit Counter and Phase Control
1613
15.3.2.2.5 CAP1-CAP4 Registers
1614
15.3.2.2.6 Interrupt Control
1614
15.3.2.2.7 Shadow Load and Lockout Control
1614
15.3.2.2.8 APWM Mode Operation
1616
15.3.3 Use Cases
1618
15.3.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
1619
15.3.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
1621
15.3.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
1623
15.3.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
1625
15.3.3.5 Application of the APWM Mode
1627
15.3.3.5.1 Simple PWM Generation (Independent Channel/s) Example
1627
15.3.3.5.2 Multichannel PWM Generation with Synchronization Example
1628
15.3.3.5.3 Multichannel PWM Generation with Phase Control Example
1631
15.3.4 Registers
1634
15.3.4.1 ECAP Registers
1634
15.3.4.1.1 TSCTR Register (offset = 0h) [reset = 0h]
1635
15.3.4.1.2 CTRPHS Register (offset = 4h) [reset = 0h]
1636
15.3.4.1.3 CAP1 Register (offset = 8h) [reset = 0h]
1637
15.3.4.1.4 CAP2 Register (offset = Ch) [reset = 0h]
1638
15.3.4.1.5 CAP3 Register (offset = 10h) [reset = 0h]
1639
15.3.4.1.6 CAP4 Register (offset = 14h) [reset = 0h]
1640
15.3.4.1.7 ECCTL1 Register (offset = 28h) [reset = 0h]
1641
15.3.4.1.8 ECCTL2 Register (offset = 2Ah) [reset = 0h]
1643
15.3.4.1.9 ECEINT Register (offset = 2Ch) [reset = 0h]
1645
15.3.4.1.10 ECFLG Register (offset = 2Eh) [reset = 0h]
1646
15.3.4.1.11 ECCLR Register (offset = 30h) [reset = 0h]
1647
15.3.4.1.12 ECFRC Register (offset = 32h) [reset = 0h]
1648
15.3.4.1.13 REVID Register (offset = 5Ch) [reset = 44D22100h]
1649
15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
1650
15.4.1 Introduction
1650
15.4.2 Functional Description
1653
15.4.2.1 EQEP Inputs
1653
15.4.2.2 Functional Description
1653
15.4.2.3 Quadrature Decoder Unit (QDU)
1655
15.4.2.3.1 Position Counter Input Modes
1656
15.4.2.3.2 eQEP Input Polarity Selection
1658
15.4.2.3.3 Position-Compare Sync Output
1658
15.4.2.4 Position Counter and Control Unit (PCCU)
1658
15.4.2.4.1 Position Counter Operating Modes
1658
15.4.2.4.2 Position Counter Latch
1661
15.4.2.4.3 Position Counter Initialization
1664
15.4.2.4.4 eQEP Position-compare Unit
1664
15.4.2.5 eQEP Edge Capture Unit
1666
15.4.2.6 eQEP Watchdog
1669
15.4.2.7 Unit Timer Base
1670
15.4.2.8 eQEP Interrupt Structure
1670
15.4.3 eQEP Registers
1672
15.4.3.1 eQEP Position Counter Register (QPOSCNT)
1673
15.4.3.2 eQEP Position Counter Initialization Register (QPOSINIT)
1673
15.4.3.3 eQEP Maximum Position Count Register (QPOSMAX)
1673
15.4.3.4 eQEP Position-Compare Register (QPOSCMP)
1674
15.4.3.5 eQEP Index Position Latch Register (QPOSILAT)
1674
15.4.3.6 eQEP Strobe Position Latch Register (QPOSSLAT)
1674
15.4.3.7 eQEP Position Counter Latch Register (QPOSLAT)
1675
15.4.3.8 eQEP Unit Timer Register (QUTMR)
1675
15.4.3.9 eQEP Unit Period Register (QUPRD)
1675
15.4.3.10 eQEP Watchdog Timer Register (QWDTMR)
1676
15.4.3.11 eQEP Watchdog Period Register (QWDPRD)
1676
15.4.3.12 QEP Decoder Control Register (QDECCTL)
1677
15.4.3.13 eQEP Control Register (QEPCTL)
1678
15.4.3.14 eQEP Capture Control Register (QCAPCTL)
1680
15.4.3.15 eQEP Position-Compare Control Register (QPOSCTL)
1681
15.4.3.16 eQEP Interrupt Enable Register (QEINT)
1682
15.4.3.17 eQEP Interrupt Flag Register (QFLG)
1683
15.4.3.18 eQEP Interrupt Clear Register (QCLR)
1684
15.4.3.19 eQEP Interrupt Force Register (QFRC)
1686
15.4.3.20 eQEP Status Register (QEPSTS)
1687
15.4.3.21 eQEP Capture Timer Register (QCTMR)
1688
15.4.3.22 eQEP Capture Period Register (QCPRD)
1688
15.4.3.23 eQEP Capture Timer Latch Register (QCTMRLAT)
1688
15.4.3.24 eQEP Capture Period Latch Register (QCPRDLAT)
1689
15.4.3.25 eQEP Revision ID Register (REVID)
1689
16 Universal Serial Bus (USB)
1690
16.1 Introduction
1691
16.1.1 Acronyms, Abbreviations, and Definitions
1691
16.1.2 USB Features
1692
16.1.3 Unsupported USB OTG and PHY Features
1693
16.2 Integration
1694
16.2.1 USB Connectivity Attributes
1694
16.2.2 USB Clock and Reset Management
1695
16.2.3 USB Pin List
1695
16.2.4 USB GPIO Details
1695
16.2.5 USB Unbonded PHY Pads
1696
16.3 Functional Description
1697
16.3.1 VBUS Voltage Sourcing Control
1697
16.3.2 Pullup/PullDown Resistors
1697
16.3.3 Role Assuming Method
1698
16.3.4 Clock, PLL, and PHY Initialization
1698
16.3.5 Indexed and Non-Indexed Register Spaces
1698
16.3.6 Dynamic FIFO Sizing
1698
16.3.7 USB Controller Host and Peripheral Modes Operation
1699
16.3.8 Protocol Description(s)
1701
16.3.8.1 USB Controller Peripheral Mode Operation
1701
16.3.8.1.1 Control Transactions:Peripheral Mode
1701
16.3.8.1.2 Bulk Transfer: Peripheral Mode
1711
16.3.8.1.3 Interrupt Transfer: Peripheral Mode
1714
16.3.8.1.4 Isochronous Transfer: Peripheral Mode
1714
16.3.8.2 USB Controller Host Mode Operation
1718
16.3.8.2.1 Control Transactions: Host Mode
1719
16.3.8.2.2 Bulk Transfer: Host Mode
1726
16.3.8.2.3 Interrupt Transfer: Host Mode
1730
16.3.8.2.4 Isochronous Transfer: Host Mode
1730
16.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA
1734
16.3.9.1 CPPI Terminology
1734
16.3.9.2 Data Structures
1735
16.3.9.2.1 Host Packet Descriptor/ Packet Descriptor (SOP Descriptor)
1735
16.3.9.2.2 Host Buffer Descriptor/Buffer Descriptor (BD)
1738
16.3.9.2.3 Teardown Descriptor
1740
16.3.9.3 Queue Manager
1742
16.3.9.3.1 Queue Types
1742
16.3.9.3.2 Free Descriptor Queue (Receive Submit Queue)
1745
16.3.9.3.3 Transmit Submit Queue
1745
16.3.9.3.4 Transmit Completion (Return) Queue
1745
16.3.9.3.5 Receive Completion (Return) Queue
1745
16.3.9.3.6 Diverting Queue Packets from one Queue to Another
1745
16.3.9.4 Memory Regions and Linking RAM
1745
16.3.9.5 Zero Length Packets
1746
16.3.9.6 CPPI DMA Scheduler
1747
16.3.9.6.1 CPPI DMA Scheduler Operation
1747
16.3.9.7 CPPI DMA State Registers
1748
16.3.9.7.1 Transmit DMA State Registers
1748
16.3.9.7.2 Receive DMA State Registers
1748
16.3.9.8 CPPI DMA Protocols Supported
1749
16.3.9.8.1 Transparent DMA Transfer
1749
16.3.9.8.2 RNDIS DMA Transfer
1749
16.3.9.8.3 Generic RNDIS DMA Transfer
1749
16.3.9.8.4 Linux CDC DMA Transfer
1750
16.3.9.9 USB Data Flow Using DMA
1750
16.3.9.9.1 Transmit USB Data Flow Using DMA
1752
16.3.9.9.2 Receive USB Data Flow Using DMA
1755
16.3.10 USB 2.0 Test Modes
1758
16.3.10.1 TEST_SE0_NAK
1758
16.3.10.2 TEST_J
1758
16.3.10.3 TEST_K
1758
16.3.10.4 TEST_PACKET
1758
16.3.10.5 FIFO_ACCESS
1759
16.3.10.6 FORCE_HOST
1759
16.4 Supported Use Cases
1759
16.5 USB Registers
1760
16.5.1 USBSS Registers
1760
16.5.1.1 REVREG Register (offset = 0h) [reset = 4EA20800h]
1762
16.5.1.2 SYSCONFIG Register (offset = 10h) [reset = 28h]
1763
16.5.1.3 IRQSTATRAW Register (offset = 24h) [reset = 0h]
1764
16.5.1.4 IRQSTAT Register (offset = 28h) [reset = 0h]
1765
16.5.1.5 IRQENABLER Register (offset = 2Ch) [reset = 0h]
1766
16.5.1.6 IRQCLEARR Register (offset = 30h) [reset = 0h]
1767
16.5.1.7 IRQDMATHOLDTX00 Register (offset = 100h) [reset = 0h]
1768
16.5.1.8 IRQDMATHOLDTX01 Register (offset = 104h) [reset = 0h]
1769
16.5.1.9 IRQDMATHOLDTX02 Register (offset = 108h) [reset = 0h]
1770
16.5.1.10 IRQDMATHOLDTX03 Register (offset = 10Ch) [reset = 0h]
1771
16.5.1.11 IRQDMATHOLDRX00 Register (offset = 110h) [reset = 0h]
1772
16.5.1.12 IRQDMATHOLDRX01 Register (offset = 114h) [reset = 0h]
1773
16.5.1.13 IRQDMATHOLDRX02 Register (offset = 118h) [reset = 0h]
1774
16.5.1.14 IRQDMATHOLDRX03 Register (offset = 11Ch) [reset = 0h]
1775
16.5.1.15 IRQDMATHOLDTX10 Register (offset = 120h) [reset = 0h]
1776
16.5.1.16 IRQDMATHOLDTX11 Register (offset = 124h) [reset = 0h]
1777
16.5.1.17 IRQDMATHOLDTX12 Register (offset = 128h) [reset = 0h]
1778
16.5.1.18 IRQDMATHOLDTX13 Register (offset = 12Ch) [reset = 0h]
1779
16.5.1.19 IRQDMATHOLDRX10 Register (offset = 130h) [reset = 0h]
1780
16.5.1.20 IRQDMATHOLDRX11 Register (offset = 134h) [reset = 0h]
1781
16.5.1.21 IRQDMATHOLDRX12 Register (offset = 138h) [reset = 0h]
1782
16.5.1.22 IRQDMATHOLDRX13 Register (offset = 13Ch) [reset = 0h]
1783
16.5.1.23 IRQDMAENABLE0 Register (offset = 140h) [reset = 0h]
1784
16.5.1.24 IRQDMAENABLE1 Register (offset = 144h) [reset = 0h]
1785
16.5.1.25 IRQFRAMETHOLDTX00 Register (offset = 200h) [reset = 0h]
1786
16.5.1.26 IRQFRAMETHOLDTX01 Register (offset = 204h) [reset = 0h]
1787
16.5.1.27 IRQFRAMETHOLDTX02 Register (offset = 208h) [reset = 0h]
1788
16.5.1.28 IRQFRAMETHOLDTX03 Register (offset = 20Ch) [reset = 0h]
1789
16.5.1.29 IRQFRAMETHOLDRX00 Register (offset = 210h) [reset = 0h]
1790
16.5.1.30 IRQFRAMETHOLDRX01 Register (offset = 214h) [reset = 0h]
1791
16.5.1.31 IRQFRAMETHOLDRX02 Register (offset = 218h) [reset = 0h]
1792
16.5.1.32 IRQFRAMETHOLDRX03 Register (offset = 21Ch) [reset = 0h]
1793
16.5.1.33 IRQFRAMETHOLDTX10 Register (offset = 220h) [reset = 0h]
1794
16.5.1.34 IRQFRAMETHOLDTX11 Register (offset = 224h) [reset = 0h]
1795
16.5.1.35 IRQFRAMETHOLDTX12 Register (offset = 228h) [reset = 0h]
1796
16.5.1.36 IRQFRAMETHOLDTX13 Register (offset = 22Ch) [reset = 0h]
1797
16.5.1.37 IRQFRAMETHOLDRX10 Register (offset = 230h) [reset = 0h]
1798
16.5.1.38 IRQFRAMETHOLDRX11 Register (offset = 234h) [reset = 0h]
1799
16.5.1.39 IRQFRAMETHOLDRX12 Register (offset = 238h) [reset = 0h]
1800
16.5.1.40 IRQFRAMETHOLDRX13 Register (offset = 23Ch) [reset = 0h]
1801
16.5.1.41 IRQFRAMEENABLE0 Register (offset = 240h) [reset = 0h]
1802
16.5.1.42 IRQFRAMEENABLE1 Register (offset = 244h) [reset = 0h]
1803
16.5.2 USB0_CTRL Registers
1803
16.5.2.1 USB0REV Register (offset = 0h) [reset = 4EA20800h]
1805
16.5.2.2 USB0CTRL Register (offset = 14h) [reset = 0h]
1806
16.5.2.3 USB0STAT Register (offset = 18h) [reset = 0h]
1808
16.5.2.4 USB0IRQMSTAT Register (offset = 20h) [reset = 0h]
1809
16.5.2.5 USB0IRQSTATRAW0 Register (offset = 28h) [reset = 0h]
1810
16.5.2.6 USB0IRQSTATRAW1 Register (offset = 2Ch) [reset = 0h]
1812
16.5.2.7 USB0IRQSTAT0 Register (offset = 30h) [reset = 0h]
1814
16.5.2.8 USB0IRQSTAT1 Register (offset = 34h) [reset = 0h]
1816
16.5.2.9 USB0IRQENABLESET0 Register (offset = 38h) [reset = 0h]
1818
16.5.2.10 USB0IRQENABLESET1 Register (offset = 3Ch) [reset = 0h]
1820
16.5.2.11 USB0IRQENABLECLR0 Register (offset = 40h) [reset = 0h]
1822
16.5.2.12 USB0IRQENABLECLR1 Register (offset = 44h) [reset = 0h]
1824
16.5.2.13 USB0TXMODE Register (offset = 70h) [reset = 0h]
1826
16.5.2.14 USB0RXMODE Register (offset = 74h) [reset = 0h]
1828
16.5.2.15 USB0GENRNDISEP1 Register (offset = 80h) [reset = 0h]
1832
16.5.2.16 USB0GENRNDISEP2 Register (offset = 84h) [reset = 0h]
1833
16.5.2.17 USB0GENRNDISEP3 Register (offset = 88h) [reset = 0h]
1834
16.5.2.18 USB0GENRNDISEP4 Register (offset = 8Ch) [reset = 0h]
1835
16.5.2.19 USB0GENRNDISEP5 Register (offset = 90h) [reset = 0h]
1836
16.5.2.20 USB0GENRNDISEP6 Register (offset = 94h) [reset = 0h]
1837
16.5.2.21 USB0GENRNDISEP7 Register (offset = 98h) [reset = 0h]
1838
16.5.2.22 USB0GENRNDISEP8 Register (offset = 9Ch) [reset = 0h]
1839
16.5.2.23 USB0GENRNDISEP9 Register (offset = A0h) [reset = 0h]
1840
16.5.2.24 USB0GENRNDISEP10 Register (offset = A4h) [reset = 0h]
1841
16.5.2.25 USB0GENRNDISEP11 Register (offset = A8h) [reset = 0h]
1842
16.5.2.26 USB0GENRNDISEP12 Register (offset = ACh) [reset = 0h]
1843
16.5.2.27 USB0GENRNDISEP13 Register (offset = B0h) [reset = 0h]
1844
16.5.2.28 USB0GENRNDISEP14 Register (offset = B4h) [reset = 0h]
1845
16.5.2.29 USB0GENRNDISEP15 Register (offset = B8h) [reset = 0h]
1846
16.5.2.30 USB0AUTOREQ Register (offset = D0h) [reset = 0h]
1847
16.5.2.31 USB0SRPFIXTIME Register (offset = D4h) [reset = 280DE80h]
1849
16.5.2.32 USB0_TDOWN Register (offset = D8h) [reset = 0h]
1850
16.5.2.33 USB0UTMI Register (offset = E0h) [reset = 200002h]
1851
16.5.2.34 USB0MGCUTMILB Register (offset = E4h) [reset = 82h]
1852
16.5.2.35 USB0MODE Register (offset = E8h) [reset = 100h]
1853
16.5.3 USB1_CTRL Registers
1853
16.5.3.1 USB1REV Register (offset = 0h) [reset = 4EA20800h]
1855
16.5.3.2 USB1CTRL Register (offset = 14h) [reset = 0h]
1856
16.5.3.3 USB1STAT Register (offset = 18h) [reset = 0h]
1858
16.5.3.4 USB1IRQMSTAT Register (offset = 20h) [reset = 0h]
1859
16.5.3.5 USB1IRQSTATRAW0 Register (offset = 28h) [reset = 0h]
1860
16.5.3.6 USB1IRQSTATRAW1 Register (offset = 2Ch) [reset = 0h]
1862
16.5.3.7 USB1IRQSTAT0 Register (offset = 30h) [reset = 0h]
1864
16.5.3.8 USB1IRQSTAT1 Register (offset = 34h) [reset = 0h]
1866
16.5.3.9 USB1IRQENABLESET0 Register (offset = 38h) [reset = 0h]
1868
16.5.3.10 USB1IRQENABLESET1 Register (offset = 3Ch) [reset = 0h]
1870
16.5.3.11 USB1IRQENABLECLR0 Register (offset = 40h) [reset = 0h]
1872
16.5.3.12 USB1IRQENABLECLR1 Register (offset = 44h) [reset = 0h]
1874
16.5.3.13 USB1TXMODE Register (offset = 70h) [reset = 0h]
1876
16.5.3.14 USB1RXMODE Register (offset = 74h) [reset = 0h]
1878
16.5.3.15 USB1GENRNDISEP1 Register (offset = 80h) [reset = 0h]
1880
16.5.3.16 USB1GENRNDISEP2 Register (offset = 84h) [reset = 0h]
1881
16.5.3.17 USB1GENRNDISEP3 Register (offset = 88h) [reset = 0h]
1882
16.5.3.18 USB1GENRNDISEP4 Register (offset = 8Ch) [reset = 0h]
1883
16.5.3.19 USB1GENRNDISEP5 Register (offset = 90h) [reset = 0h]
1884
16.5.3.20 USB1GENRNDISEP6 Register (offset = 94h) [reset = 0h]
1885
16.5.3.21 USB1GENRNDISEP7 Register (offset = 98h) [reset = 0h]
1886
16.5.3.22 USB1GENRNDISEP8 Register (offset = 9Ch) [reset = 0h]
1887
16.5.3.23 USB1GENRNDISEP9 Register (offset = A0h) [reset = 0h]
1888
16.5.3.24 USB1GENRNDISEP10 Register (offset = A4h) [reset = 0h]
1889
16.5.3.25 USB1GENRNDISEP11 Register (offset = A8h) [reset = 0h]
1890
16.5.3.26 USB1GENRNDISEP12 Register (offset = ACh) [reset = 0h]
1891
16.5.3.27 USB1GENRNDISEP13 Register (offset = B0h) [reset = 0h]
1892
16.5.3.28 USB1GENRNDISEP14 Register (offset = B4h) [reset = 0h]
1893
16.5.3.29 USB1GENRNDISEP15 Register (offset = B8h) [reset = 0h]
1894
16.5.3.30 USB1AUTOREQ Register (offset = D0h) [reset = 0h]
1895
16.5.3.31 USB1SRPFIXTIME Register (offset = D4h) [reset = 280DE80h]
1897
16.5.3.32 USB1TDOWN Register (offset = D8h) [reset = 0h]
1898
16.5.3.33 USB1UTMI Register (offset = E0h) [reset = 200002h]
1899
16.5.3.34 USB1UTMILB Register (offset = E4h) [reset = 82h]
1900
16.5.3.35 USB1MODE Register (offset = E8h) [reset = 100h]
1901
16.5.4 USB2PHY Registers
1901
16.5.4.1 Termination_control Register (offset = 0h) [reset = 1000800h]
1903
16.5.4.2 RX_CALIB Register (offset = 4h) [reset = 0h]
1904
16.5.4.3 DLLHS_2 Register (offset = 8h) [reset = 1Fh]
1906
16.5.4.4 RX_TEST_2 Register (offset = Ch) [reset = 0h]
1907
16.5.4.5 CHRG_DET Register (offset = 14h) [reset = 0h]
1908
16.5.4.6 PWR_CNTL Register (offset = 18h) [reset = 400000h]
1910
16.5.4.7 UTMI_INTERFACE_CNTL_1 Register (offset = 1Ch) [reset = 0h]
1911
16.5.4.8 UTMI_INTERFACE_CNTL_2 Register (offset = 20h) [reset = 0h]
1912
16.5.4.9 BIST Register (offset = 24h) [reset = 0h]
1914
16.5.4.10 BIST_CRC Register (offset = 28h) [reset = 0h]
1915
16.5.4.11 CDR_BIST2 Register (offset = 2Ch) [reset = 0h]
1916
16.5.4.12 GPIO Register (offset = 30h) [reset = 0h]
1917
16.5.4.13 DLLHS Register (offset = 34h) [reset = 8000h]
1918
16.5.4.14 USB2PHYCM_CONFIG Register (offset = 3Ch) [reset = 0h]
1919
16.5.4.15 AD_INTERFACE_REG1 Register (offset = 44h) [reset = 0h]
1920
16.5.4.16 AD_INTERFACE_REG2 Register (offset = 48h) [reset = 0h]
1922
16.5.4.17 AD_INTERFACE_REG3 Register (offset = 4Ch) [reset = 0h]
1924
16.5.4.18 ANA_CONFIG2 Register (offset = 54h) [reset = 0h]
1925
16.5.5 CPPI_DMA Registers
1925
16.5.5.1 DMAREVID Register (offset = 0h) [reset = 530901h]
1929
16.5.5.2 TDFDQ Register (offset = 4h) [reset = 0h]
1930
16.5.5.3 DMAEMU Register (offset = 8h) [reset = 0h]
1931
16.5.5.4 TXGCR0 Register (offset = 800h) [reset = 0h]
1932
16.5.5.5 RXGCR0 Register (offset = 808h) [reset = 0h]
1933
16.5.5.6 RXHPCRA0 Register (offset = 80Ch) [reset = 0h]
1935
16.5.5.7 RXHPCRB0 Register (offset = 810h) [reset = 0h]
1936
16.5.5.8 TXGCR1 Register (offset = 820h) [reset = 0h]
1937
16.5.5.9 RXGCR1 Register (offset = 828h) [reset = 0h]
1938
16.5.5.10 RXHPCRA1 Register (offset = 82Ch) [reset = 0h]
1940
16.5.5.11 RXHPCRB1 Register (offset = 830h) [reset = 0h]
1941
16.5.5.12 TXGCR2 Register (offset = 840h) [reset = 0h]
1942
16.5.5.13 RXGCR2 Register (offset = 848h) [reset = 0h]
1943
16.5.5.14 RXHPCRA2 Register (offset = 84Ch) [reset = 0h]
1945
16.5.5.15 RXHPCRB2 Register (offset = 850h) [reset = 0h]
1946
16.5.5.16 TXGCR3 Register (offset = 860h) [reset = 0h]
1947
16.5.5.17 RXGCR3 Register (offset = 868h) [reset = 0h]
1948
16.5.5.18 RXHPCRA3 Register (offset = 86Ch) [reset = 0h]
1950
16.5.5.19 RXHPCRB3 Register (offset = 870h) [reset = 0h]
1951
16.5.5.20 TXGCR4 Register (offset = 880h) [reset = 0h]
1952
16.5.5.21 RXGCR4 Register (offset = 888h) [reset = 0h]
1953
16.5.5.22 RXHPCRA4 Register (offset = 88Ch) [reset = 0h]
1955
16.5.5.23 RXHPCRB4 Register (offset = 890h) [reset = 0h]
1956
16.5.5.24 TXGCR5 Register (offset = 8A0h) [reset = 0h]
1957
16.5.5.25 RXGCR5 Register (offset = 8A8h) [reset = 0h]
1958
16.5.5.26 RXHPCRA5 Register (offset = 8ACh) [reset = 0h]
1960
16.5.5.27 RXHPCRB5 Register (offset = 8B0h) [reset = 0h]
1961
16.5.5.28 TXGCR6 Register (offset = 8C0h) [reset = 0h]
1962
16.5.5.29 RXGCR6 Register (offset = 8C8h) [reset = 0h]
1963
16.5.5.30 RXHPCRA6 Register (offset = 8CCh) [reset = 0h]
1965
16.5.5.31 RXHPCRB6 Register (offset = 8D0h) [reset = 0h]
1966
16.5.5.32 TXGCR7 Register (offset = 8E0h) [reset = 0h]
1967
16.5.5.33 RXGCR7 Register (offset = 8E8h) [reset = 0h]
1968
16.5.5.34 RXHPCRA7 Register (offset = 8ECh) [reset = 0h]
1970
16.5.5.35 RXHPCRB7 Register (offset = 8F0h) [reset = 0h]
1971
16.5.5.36 TXGCR8 Register (offset = 900h) [reset = 0h]
1972
16.5.5.37 RXGCR8 Register (offset = 908h) [reset = 0h]
1973
16.5.5.38 RXHPCRA8 Register (offset = 90Ch) [reset = 0h]
1975
16.5.5.39 RXHPCRB8 Register (offset = 910h) [reset = 0h]
1976
16.5.5.40 TXGCR9 Register (offset = 920h) [reset = 0h]
1977
16.5.5.41 RXGCR9 Register (offset = 928h) [reset = 0h]
1978
16.5.5.42 RXHPCRA9 Register (offset = 92Ch) [reset = 0h]
1980
16.5.5.43 RXHPCRB9 Register (offset = 930h) [reset = 0h]
1981
16.5.5.44 TXGCR10 Register (offset = 940h) [reset = 0h]
1982
16.5.5.45 RXGCR10 Register (offset = 948h) [reset = 0h]
1983
16.5.5.46 RXHPCRA10 Register (offset = 94Ch) [reset = 0h]
1985
16.5.5.47 RXHPCRB10 Register (offset = 950h) [reset = 0h]
1986
16.5.5.48 TXGCR11 Register (offset = 960h) [reset = 0h]
1987
16.5.5.49 RXGCR11 Register (offset = 968h) [reset = 0h]
1988
16.5.5.50 RXHPCRA11 Register (offset = 96Ch) [reset = 0h]
1990
16.5.5.51 RXHPCRB11 Register (offset = 970h) [reset = 0h]
1991
16.5.5.52 TXGCR12 Register (offset = 980h) [reset = 0h]
1992
16.5.5.53 RXGCR12 Register (offset = 988h) [reset = 0h]
1993
16.5.5.54 RXHPCRA12 Register (offset = 98Ch) [reset = 0h]
1995
16.5.5.55 RXHPCRB12 Register (offset = 990h) [reset = 0h]
1996
16.5.5.56 TXGCR13 Register (offset = 9A0h) [reset = 0h]
1997
16.5.5.57 RXGCR13 Register (offset = 9A8h) [reset = 0h]
1998
16.5.5.58 RXHPCRA13 Register (offset = 9ACh) [reset = 0h]
2000
16.5.5.59 RXHPCRB13 Register (offset = 9B0h) [reset = 0h]
2001
16.5.5.60 TXGCR14 Register (offset = 9C0h) [reset = 0h]
2002
16.5.5.61 RXGCR14 Register (offset = 9C8h) [reset = 0h]
2003
16.5.5.62 RXHPCRA14 Register (offset = 9CCh) [reset = 0h]
2005
16.5.5.63 RXHPCRB14 Register (offset = 9D0h) [reset = 0h]
2006
16.5.5.64 TXGCR15 Register (offset = 9E0h) [reset = 0h]
2007
16.5.5.65 RXGCR15 Register (offset = 9E8h) [reset = 0h]
2008
16.5.5.66 RXHPCRA15 Register (offset = 9ECh) [reset = 0h]
2010
16.5.5.67 RXHPCRB15 Register (offset = 9F0h) [reset = 0h]
2011
16.5.5.68 TXGCR16 Register (offset = A00h) [reset = 0h]
2012
16.5.5.69 RXGCR16 Register (offset = A08h) [reset = 0h]
2013
16.5.5.70 RXHPCRA16 Register (offset = A0Ch) [reset = 0h]
2015
16.5.5.71 RXHPCRB16 Register (offset = A10h) [reset = 0h]
2016
16.5.5.72 TXGCR17 Register (offset = A20h) [reset = 0h]
2017
16.5.5.73 RXGCR17 Register (offset = A28h) [reset = 0h]
2018
16.5.5.74 RXHPCRA17 Register (offset = A2Ch) [reset = 0h]
2020
16.5.5.75 RXHPCRB17 Register (offset = A30h) [reset = 0h]
2021
16.5.5.76 TXGCR18 Register (offset = A40h) [reset = 0h]
2022
16.5.5.77 RXGCR18 Register (offset = A48h) [reset = 0h]
2023
16.5.5.78 RXHPCRA18 Register (offset = A4Ch) [reset = 0h]
2025
16.5.5.79 RXHPCRB18 Register (offset = A50h) [reset = 0h]
2026
16.5.5.80 TXGCR19 Register (offset = A60h) [reset = 0h]
2027
16.5.5.81 RXGCR19 Register (offset = A68h) [reset = 0h]
2028
16.5.5.82 RXHPCRA19 Register (offset = A6Ch) [reset = 0h]
2030
16.5.5.83 RXHPCRB19 Register (offset = A70h) [reset = 0h]
2031
16.5.5.84 TXGCR20 Register (offset = A80h) [reset = 0h]
2032
16.5.5.85 RXGCR20 Register (offset = A88h) [reset = 0h]
2033
16.5.5.86 RXHPCRA20 Register (offset = A8Ch) [reset = 0h]
2035
16.5.5.87 RXHPCRB20 Register (offset = A90h) [reset = 0h]
2036
16.5.5.88 TXGCR21 Register (offset = AA0h) [reset = 0h]
2037
16.5.5.89 RXGCR21 Register (offset = AA8h) [reset = 0h]
2038
16.5.5.90 RXHPCRA21 Register (offset = AACh) [reset = 0h]
2040
16.5.5.91 RXHPCRB21 Register (offset = AB0h) [reset = 0h]
2041
16.5.5.92 TXGCR22 Register (offset = AC0h) [reset = 0h]
2042
16.5.5.93 RXGCR22 Register (offset = AC8h) [reset = 0h]
2043
16.5.5.94 RXHPCRA22 Register (offset = ACCh) [reset = 0h]
2045
16.5.5.95 RXHPCRB22 Register (offset = AD0h) [reset = 0h]
2046
16.5.5.96 TXGCR23 Register (offset = AE0h) [reset = 0h]
2047
16.5.5.97 RXGCR23 Register (offset = AE8h) [reset = 0h]
2048
16.5.5.98 RXHPCRA23 Register (offset = AECh) [reset = 0h]
2050
16.5.5.99 RXHPCRB23 Register (offset = AF0h) [reset = 0h]
2051
16.5.5.100 TXGCR24 Register (offset = B00h) [reset = 0h]
2052
16.5.5.101 RXGCR24 Register (offset = B08h) [reset = 0h]
2053
16.5.5.102 RXHPCRA24 Register (offset = B0Ch) [reset = 0h]
2055
16.5.5.103 RXHPCRB24 Register (offset = B10h) [reset = 0h]
2056
16.5.5.104 TXGCR25 Register (offset = B20h) [reset = 0h]
2057
16.5.5.105 RXGCR25 Register (offset = B28h) [reset = 0h]
2058
16.5.5.106 RXHPCRA25 Register (offset = B2Ch) [reset = 0h]
2060
16.5.5.107 RXHPCRB25 Register (offset = B30h) [reset = 0h]
2061
16.5.5.108 TXGCR26 Register (offset = B40h) [reset = 0h]
2062
16.5.5.109 RXGCR26 Register (offset = B48h) [reset = 0h]
2063
16.5.5.110 RXHPCRA26 Register (offset = B4Ch) [reset = 0h]
2065
16.5.5.111 RXHPCRB26 Register (offset = B50h) [reset = 0h]
2066
16.5.5.112 TXGCR27 Register (offset = B60h) [reset = 0h]
2067
16.5.5.113 RXGCR27 Register (offset = B68h) [reset = 0h]
2068
16.5.5.114 RXHPCRA27 Register (offset = B6Ch) [reset = 0h]
2070
16.5.5.115 RXHPCRB27 Register (offset = B70h) [reset = 0h]
2071
16.5.5.116 TXGCR28 Register (offset = B80h) [reset = 0h]
2072
16.5.5.117 RXGCR28 Register (offset = B88h) [reset = 0h]
2073
16.5.5.118 RXHPCRA28 Register (offset = B8Ch) [reset = 0h]
2075
16.5.5.119 RXHPCRB28 Register (offset = B90h) [reset = 0h]
2076
16.5.5.120 TXGCR29 Register (offset = BA0h) [reset = 0h]
2077
16.5.5.121 RXGCR29 Register (offset = BA8h) [reset = 0h]
2078
16.5.5.122 RXHPCRA29 Register (offset = BACh) [reset = 0h]
2080
16.5.5.123 RXHPCRB29 Register (offset = BB0h) [reset = 0h]
2081
16.5.6 CPPI_DMA_SCHEDULER Registers
2081
16.5.6.1 DMA_SCHED_CTRL Register (offset = 0h) [reset = 0h]
2082
16.5.6.2 WORDx Register (offset = 800h to 900h) [reset = 0h]
2083
16.5.7 QUEUE_MGR Registers
2084
16.5.7.1 QMGRREVID Register (offset = 0h) [reset = 4E530800h]
2109
16.5.7.2 QMGRRST Register (offset = 8h) [reset = 0h]
2110
16.5.7.3 FDBSC0 Register (offset = 20h) [reset = 0h]
2111
16.5.7.4 FDBSC1 Register (offset = 24h) [reset = 0h]
2112
16.5.7.5 FDBSC2 Register (offset = 28h) [reset = 0h]
2113
16.5.7.6 FDBSC3 Register (offset = 2Ch) [reset = 0h]
2114
16.5.7.7 FDBSC4 Register (offset = 30h) [reset = 0h]
2115
16.5.7.8 FDBSC5 Register (offset = 34h) [reset = 0h]
2116
16.5.7.9 FDBSC6 Register (offset = 38h) [reset = 0h]
2117
16.5.7.10 FDBSC7 Register (offset = 3Ch) [reset = 0h]
2118
16.5.7.11 LRAM0BASE Register (offset = 80h) [reset = 0h]
2119
16.5.7.12 LRAM0SIZE Register (offset = 84h) [reset = 0h]
2120
16.5.7.13 LRAM1BASE Register (offset = 88h) [reset = 0h]
2121
16.5.7.14 PEND0 Register (offset = 90h) [reset = 0h]
2122
16.5.7.15 PEND1 Register (offset = 94h) [reset = 0h]
2123
16.5.7.16 PEND2 Register (offset = 98h) [reset = 0h]
2124
16.5.7.17 PEND3 Register (offset = 9Ch) [reset = 0h]
2125
16.5.7.18 PEND4 Register (offset = A0h) [reset = 0h]
2126
16.5.7.19 QMEMRBASE0 Register (offset = 1000h) [reset = 0h]
2127
16.5.7.20 QMEMCTRL0 Register (offset = 1004h) [reset = 0h]
2128
16.5.7.21 QMEMRBASE1 Register (offset = 1010h) [reset = 0h]
2129
16.5.7.22 QMEMCTRL1 Register (offset = 1014h) [reset = 0h]
2130
16.5.7.23 QMEMRBASE2 Register (offset = 1020h) [reset = 0h]
2131
16.5.7.24 QMEMCTRL2 Register (offset = 1024h) [reset = 0h]
2132
16.5.7.25 QMEMRBASE3 Register (offset = 1030h) [reset = 0h]
2133
16.5.7.26 QMEMCTRL3 Register (offset = 1034h) [reset = 0h]
2134
16.5.7.27 QMEMRBASE4 Register (offset = 1040h) [reset = 0h]
2135
16.5.7.28 QMEMCTRL4 Register (offset = 1044h) [reset = 0h]
2136
16.5.7.29 QMEMRBASE5 Register (offset = 1050h) [reset = 0h]
2137
16.5.7.30 QMEMCTRL5 Register (offset = 1054h) [reset = 0h]
2138
16.5.7.31 QMEMRBASE6 Register (offset = 1060h) [reset = 0h]
2139
16.5.7.32 QMEMCTRL6 Register (offset = 1064h) [reset = 0h]
2140
16.5.7.33 QMEMRBASE7 Register (offset = 1070h) [reset = 0h]
2141
16.5.7.34 QMEMCTRL7 Register (offset = 1074h) [reset = 0h]
2142
16.5.7.35 QUEUE_0_A Register (offset = 2000h) [reset = 0h]
2143
16.5.7.36 QUEUE_0_B Register (offset = 2004h) [reset = 0h]
2144
16.5.7.37 QUEUE_0_C Register (offset = 2008h) [reset = 0h]
2145
16.5.7.38 QUEUE_0_D Register (offset = 200Ch) [reset = 0h]
2146
16.5.7.39 QUEUE_1_A Register (offset = 2010h) [reset = 0h]
2147
16.5.7.40 QUEUE_1_B Register (offset = 2014h) [reset = 0h]
2148
16.5.7.41 QUEUE_1_C Register (offset = 2018h) [reset = 0h]
2149
16.5.7.42 QUEUE_1_D Register (offset = 201Ch) [reset = 0h]
2150
16.5.7.43 QUEUE_2_A Register (offset = 2020h) [reset = 0h]
2151
16.5.7.44 QUEUE_2_B Register (offset = 2024h) [reset = 0h]
2152
16.5.7.45 QUEUE_2_C Register (offset = 2028h) [reset = 0h]
2153
16.5.7.46 QUEUE_2_D Register (offset = 202Ch) [reset = 0h]
2154
16.5.7.47 QUEUE_3_A Register (offset = 2030h) [reset = 0h]
2155
16.5.7.48 QUEUE_3_B Register (offset = 2034h) [reset = 0h]
2156
16.5.7.49 QUEUE_3_C Register (offset = 2038h) [reset = 0h]
2157
16.5.7.50 QUEUE_3_D Register (offset = 203Ch) [reset = 0h]
2158
16.5.7.51 QUEUE_4_A Register (offset = 2040h) [reset = 0h]
2159
16.5.7.52 QUEUE_4_B Register (offset = 2044h) [reset = 0h]
2160
16.5.7.53 QUEUE_4_C Register (offset = 2048h) [reset = 0h]
2161
16.5.7.54 QUEUE_4_D Register (offset = 204Ch) [reset = 0h]
2162
16.5.7.55 QUEUE_5_A Register (offset = 2050h) [reset = 0h]
2163
16.5.7.56 QUEUE_5_B Register (offset = 2054h) [reset = 0h]
2164
16.5.7.57 QUEUE_5_C Register (offset = 2058h) [reset = 0h]
2165
16.5.7.58 QUEUE_5_D Register (offset = 205Ch) [reset = 0h]
2166
16.5.7.59 QUEUE_6_A Register (offset = 2060h) [reset = 0h]
2167
16.5.7.60 QUEUE_6_B Register (offset = 2064h) [reset = 0h]
2168
16.5.7.61 QUEUE_6_C Register (offset = 2068h) [reset = 0h]
2169
16.5.7.62 QUEUE_6_D Register (offset = 206Ch) [reset = 0h]
2170
16.5.7.63 QUEUE_7_A Register (offset = 2070h) [reset = 0h]
2171
16.5.7.64 QUEUE_7_B Register (offset = 2074h) [reset = 0h]
2172
16.5.7.65 QUEUE_7_C Register (offset = 2078h) [reset = 0h]
2173
16.5.7.66 QUEUE_7_D Register (offset = 207Ch) [reset = 0h]
2174
16.5.7.67 QUEUE_8_A Register (offset = 2080h) [reset = 0h]
2175
16.5.7.68 QUEUE_8_B Register (offset = 2084h) [reset = 0h]
2176
16.5.7.69 QUEUE_8_C Register (offset = 2088h) [reset = 0h]
2177
16.5.7.70 QUEUE_8_D Register (offset = 208Ch) [reset = 0h]
2178
16.5.7.71 QUEUE_9_A Register (offset = 2090h) [reset = 0h]
2179
16.5.7.72 QUEUE_9_B Register (offset = 2094h) [reset = 0h]
2180
16.5.7.73 QUEUE_9_C Register (offset = 2098h) [reset = 0h]
2181
16.5.7.74 QUEUE_9_D Register (offset = 209Ch) [reset = 0h]
2182
16.5.7.75 QUEUE_10_A Register (offset = 20A0h) [reset = 0h]
2183
16.5.7.76 QUEUE_10_B Register (offset = 20A4h) [reset = 0h]
2184
16.5.7.77 QUEUE_10_C Register (offset = 20A8h) [reset = 0h]
2185
16.5.7.78 QUEUE_10_D Register (offset = 20ACh) [reset = 0h]
2186
16.5.7.79 QUEUE_11_A Register (offset = 20B0h) [reset = 0h]
2187
16.5.7.80 QUEUE_11_B Register (offset = 20B4h) [reset = 0h]
2188
16.5.7.81 QUEUE_11_C Register (offset = 20B8h) [reset = 0h]
2189
16.5.7.82 QUEUE_11_D Register (offset = 20BCh) [reset = 0h]
2190
16.5.7.83 QUEUE_12_A Register (offset = 20C0h) [reset = 0h]
2191
16.5.7.84 QUEUE_12_B Register (offset = 20C4h) [reset = 0h]
2192
16.5.7.85 QUEUE_12_C Register (offset = 20C8h) [reset = 0h]
2193
16.5.7.86 QUEUE_12_D Register (offset = 20CCh) [reset = 0h]
2194
16.5.7.87 QUEUE_13_A Register (offset = 20D0h) [reset = 0h]
2195
16.5.7.88 QUEUE_13_B Register (offset = 20D4h) [reset = 0h]
2196
16.5.7.89 QUEUE_13_C Register (offset = 20D8h) [reset = 0h]
2197
16.5.7.90 QUEUE_13_D Register (offset = 20DCh) [reset = 0h]
2198
16.5.7.91 QUEUE_14_A Register (offset = 20E0h) [reset = 0h]
2199
16.5.7.92 QUEUE_14_B Register (offset = 20E4h) [reset = 0h]
2200
16.5.7.93 QUEUE_14_C Register (offset = 20E8h) [reset = 0h]
2201
16.5.7.94 QUEUE_14_D Register (offset = 20ECh) [reset = 0h]
2202
16.5.7.95 QUEUE_15_A Register (offset = 20F0h) [reset = 0h]
2203
16.5.7.96 QUEUE_15_B Register (offset = 20F4h) [reset = 0h]
2204
16.5.7.97 QUEUE_15_C Register (offset = 20F8h) [reset = 0h]
2205
16.5.7.98 QUEUE_15_D Register (offset = 20FCh) [reset = 0h]
2206
16.5.7.99 QUEUE_16_A Register (offset = 2100h) [reset = 0h]
2207
16.5.7.100 QUEUE_16_B Register (offset = 2104h) [reset = 0h]
2208
16.5.7.101 QUEUE_16_C Register (offset = 2108h) [reset = 0h]
2209
16.5.7.102 QUEUE_16_D Register (offset = 210Ch) [reset = 0h]
2210
16.5.7.103 QUEUE_17_A Register (offset = 2110h) [reset = 0h]
2211
16.5.7.104 QUEUE_17_B Register (offset = 2114h) [reset = 0h]
2212
16.5.7.105 QUEUE_17_C Register (offset = 2118h) [reset = 0h]
2213
16.5.7.106 QUEUE_17_D Register (offset = 211Ch) [reset = 0h]
2214
16.5.7.107 QUEUE_18_A Register (offset = 2120h) [reset = 0h]
2215
16.5.7.108 QUEUE_18_B Register (offset = 2124h) [reset = 0h]
2216
16.5.7.109 QUEUE_18_C Register (offset = 2128h) [reset = 0h]
2217
16.5.7.110 QUEUE_18_D Register (offset = 212Ch) [reset = 0h]
2218
16.5.7.111 QUEUE_19_A Register (offset = 2130h) [reset = 0h]
2219
16.5.7.112 QUEUE_19_B Register (offset = 2134h) [reset = 0h]
2220
16.5.7.113 QUEUE_19_C Register (offset = 2138h) [reset = 0h]
2221
16.5.7.114 QUEUE_19_D Register (offset = 213Ch) [reset = 0h]
2222
16.5.7.115 QUEUE_20_A Register (offset = 2140h) [reset = 0h]
2223
16.5.7.116 QUEUE_20_B Register (offset = 2144h) [reset = 0h]
2224
16.5.7.117 QUEUE_20_C Register (offset = 2148h) [reset = 0h]
2225
16.5.7.118 QUEUE_20_D Register (offset = 214Ch) [reset = 0h]
2226
16.5.7.119 QUEUE_21_A Register (offset = 2150h) [reset = 0h]
2227
16.5.7.120 QUEUE_21_B Register (offset = 2154h) [reset = 0h]
2228
16.5.7.121 QUEUE_21_C Register (offset = 2158h) [reset = 0h]
2229
16.5.7.122 QUEUE_21_D Register (offset = 215Ch) [reset = 0h]
2230
16.5.7.123 QUEUE_22_A Register (offset = 2160h) [reset = 0h]
2231
16.5.7.124 QUEUE_22_B Register (offset = 2164h) [reset = 0h]
2232
16.5.7.125 QUEUE_22_C Register (offset = 2168h) [reset = 0h]
2233
16.5.7.126 QUEUE_22_D Register (offset = 216Ch) [reset = 0h]
2234
16.5.7.127 QUEUE_23_A Register (offset = 2170h) [reset = 0h]
2235
16.5.7.128 QUEUE_23_B Register (offset = 2174h) [reset = 0h]
2236
16.5.7.129 QUEUE_23_C Register (offset = 2178h) [reset = 0h]
2237
16.5.7.130 QUEUE_23_D Register (offset = 217Ch) [reset = 0h]
2238
16.5.7.131 QUEUE_24_A Register (offset = 2180h) [reset = 0h]
2239
16.5.7.132 QUEUE_24_B Register (offset = 2184h) [reset = 0h]
2240
16.5.7.133 QUEUE_24_C Register (offset = 2188h) [reset = 0h]
2241
16.5.7.134 QUEUE_24_D Register (offset = 218Ch) [reset = 0h]
2242
16.5.7.135 QUEUE_25_A Register (offset = 2190h) [reset = 0h]
2243
16.5.7.136 QUEUE_25_B Register (offset = 2194h) [reset = 0h]
2244
16.5.7.137 QUEUE_25_C Register (offset = 2198h) [reset = 0h]
2245
16.5.7.138 QUEUE_25_D Register (offset = 219Ch) [reset = 0h]
2246
16.5.7.139 QUEUE_26_A Register (offset = 21A0h) [reset = 0h]
2247
16.5.7.140 QUEUE_26_B Register (offset = 21A4h) [reset = 0h]
2248
16.5.7.141 QUEUE_26_C Register (offset = 21A8h) [reset = 0h]
2249
16.5.7.142 QUEUE_26_D Register (offset = 21ACh) [reset = 0h]
2250
16.5.7.143 QUEUE_27_A Register (offset = 21B0h) [reset = 0h]
2251
16.5.7.144 QUEUE_27_B Register (offset = 21B4h) [reset = 0h]
2252
16.5.7.145 QUEUE_27_C Register (offset = 21B8h) [reset = 0h]
2253
16.5.7.146 QUEUE_27_D Register (offset = 21BCh) [reset = 0h]
2254
16.5.7.147 QUEUE_28_A Register (offset = 21C0h) [reset = 0h]
2255
16.5.7.148 QUEUE_28_B Register (offset = 21C4h) [reset = 0h]
2256
16.5.7.149 QUEUE_28_C Register (offset = 21C8h) [reset = 0h]
2257
16.5.7.150 QUEUE_28_D Register (offset = 21CCh) [reset = 0h]
2258
16.5.7.151 QUEUE_29_A Register (offset = 21D0h) [reset = 0h]
2259
16.5.7.152 QUEUE_29_B Register (offset = 21D4h) [reset = 0h]
2260
16.5.7.153 QUEUE_29_C Register (offset = 21D8h) [reset = 0h]
2261
16.5.7.154 QUEUE_29_D Register (offset = 21DCh) [reset = 0h]
2262
16.5.7.155 QUEUE_30_A Register (offset = 21E0h) [reset = 0h]
2263
16.5.7.156 QUEUE_30_B Register (offset = 21E4h) [reset = 0h]
2264
16.5.7.157 QUEUE_30_C Register (offset = 21E8h) [reset = 0h]
2265
16.5.7.158 QUEUE_30_D Register (offset = 21ECh) [reset = 0h]
2266
16.5.7.159 QUEUE_31_A Register (offset = 21F0h) [reset = 0h]
2267
16.5.7.160 QUEUE_31_B Register (offset = 21F4h) [reset = 0h]
2268
16.5.7.161 QUEUE_31_C Register (offset = 21F8h) [reset = 0h]
2269
16.5.7.162 QUEUE_31_D Register (offset = 21FCh) [reset = 0h]
2270
16.5.7.163 QUEUE_32_A Register (offset = 2200h) [reset = 0h]
2271
16.5.7.164 QUEUE_32_B Register (offset = 2204h) [reset = 0h]
2272
16.5.7.165 QUEUE_32_C Register (offset = 2208h) [reset = 0h]
2273
16.5.7.166 QUEUE_32_D Register (offset = 220Ch) [reset = 0h]
2274
16.5.7.167 QUEUE_33_A Register (offset = 2210h) [reset = 0h]
2275
16.5.7.168 QUEUE_33_B Register (offset = 2214h) [reset = 0h]
2276
16.5.7.169 QUEUE_33_C Register (offset = 2218h) [reset = 0h]
2277
16.5.7.170 QUEUE_33_D Register (offset = 221Ch) [reset = 0h]
2278
16.5.7.171 QUEUE_34_A Register (offset = 2220h) [reset = 0h]
2279
16.5.7.172 QUEUE_34_B Register (offset = 2224h) [reset = 0h]
2280
16.5.7.173 QUEUE_34_C Register (offset = 2228h) [reset = 0h]
2281
16.5.7.174 QUEUE_34_D Register (offset = 222Ch) [reset = 0h]
2282
16.5.7.175 QUEUE_35_A Register (offset = 2230h) [reset = 0h]
2283
16.5.7.176 QUEUE_35_B Register (offset = 2234h) [reset = 0h]
2284
16.5.7.177 QUEUE_35_C Register (offset = 2238h) [reset = 0h]
2285
16.5.7.178 QUEUE_35_D Register (offset = 223Ch) [reset = 0h]
2286
16.5.7.179 QUEUE_36_A Register (offset = 2240h) [reset = 0h]
2287
16.5.7.180 QUEUE_36_B Register (offset = 2244h) [reset = 0h]
2288
16.5.7.181 QUEUE_36_C Register (offset = 2248h) [reset = 0h]
2289
16.5.7.182 QUEUE_36_D Register (offset = 224Ch) [reset = 0h]
2290
16.5.7.183 QUEUE_37_A Register (offset = 2250h) [reset = 0h]
2291
16.5.7.184 QUEUE_37_B Register (offset = 2254h) [reset = 0h]
2292
16.5.7.185 QUEUE_37_C Register (offset = 2258h) [reset = 0h]
2293
16.5.7.186 QUEUE_37_D Register (offset = 225Ch) [reset = 0h]
2294
16.5.7.187 QUEUE_38_A Register (offset = 2260h) [reset = 0h]
2295
16.5.7.188 QUEUE_38_B Register (offset = 2264h) [reset = 0h]
2296
16.5.7.189 QUEUE_38_C Register (offset = 2268h) [reset = 0h]
2297
16.5.7.190 QUEUE_38_D Register (offset = 226Ch) [reset = 0h]
2298
16.5.7.191 QUEUE_39_A Register (offset = 2270h) [reset = 0h]
2299
16.5.7.192 QUEUE_39_B Register (offset = 2274h) [reset = 0h]
2300
16.5.7.193 QUEUE_39_C Register (offset = 2278h) [reset = 0h]
2301
16.5.7.194 QUEUE_39_D Register (offset = 227Ch) [reset = 0h]
2302
16.5.7.195 QUEUE_40_A Register (offset = 2280h) [reset = 0h]
2303
16.5.7.196 QUEUE_40_B Register (offset = 2284h) [reset = 0h]
2304
16.5.7.197 QUEUE_40_C Register (offset = 2288h) [reset = 0h]
2305
16.5.7.198 QUEUE_40_D Register (offset = 228Ch) [reset = 0h]
2306
16.5.7.199 QUEUE_41_A Register (offset = 2290h) [reset = 0h]
2307
16.5.7.200 QUEUE_41_B Register (offset = 2294h) [reset = 0h]
2308
16.5.7.201 QUEUE_41_C Register (offset = 2298h) [reset = 0h]
2309
16.5.7.202 QUEUE_41_D Register (offset = 229Ch) [reset = 0h]
2310
16.5.7.203 QUEUE_42_A Register (offset = 22A0h) [reset = 0h]
2311
16.5.7.204 QUEUE_42_B Register (offset = 22A4h) [reset = 0h]
2312
16.5.7.205 QUEUE_42_C Register (offset = 22A8h) [reset = 0h]
2313
16.5.7.206 QUEUE_42_D Register (offset = 22ACh) [reset = 0h]
2314
16.5.7.207 QUEUE_43_A Register (offset = 22B0h) [reset = 0h]
2315
16.5.7.208 QUEUE_43_B Register (offset = 22B4h) [reset = 0h]
2316
16.5.7.209 QUEUE_43_C Register (offset = 22B8h) [reset = 0h]
2317
16.5.7.210 QUEUE_43_D Register (offset = 22BCh) [reset = 0h]
2318
16.5.7.211 QUEUE_44_A Register (offset = 22C0h) [reset = 0h]
2319
16.5.7.212 QUEUE_44_B Register (offset = 22C4h) [reset = 0h]
2320
16.5.7.213 QUEUE_44_C Register (offset = 22C8h) [reset = 0h]
2321
16.5.7.214 QUEUE_44_D Register (offset = 22CCh) [reset = 0h]
2322
16.5.7.215 QUEUE_45_A Register (offset = 22D0h) [reset = 0h]
2323
16.5.7.216 QUEUE_45_B Register (offset = 22D4h) [reset = 0h]
2324
16.5.7.217 QUEUE_45_C Register (offset = 22D8h) [reset = 0h]
2325
16.5.7.218 QUEUE_45_D Register (offset = 22DCh) [reset = 0h]
2326
16.5.7.219 QUEUE_46_A Register (offset = 22E0h) [reset = 0h]
2327
16.5.7.220 QUEUE_46_B Register (offset = 22E4h) [reset = 0h]
2328
16.5.7.221 QUEUE_46_C Register (offset = 22E8h) [reset = 0h]
2329
16.5.7.222 QUEUE_46_D Register (offset = 22ECh) [reset = 0h]
2330
16.5.7.223 QUEUE_47_A Register (offset = 22F0h) [reset = 0h]
2331
16.5.7.224 QUEUE_47_B Register (offset = 22F4h) [reset = 0h]
2332
16.5.7.225 QUEUE_47_C Register (offset = 22F8h) [reset = 0h]
2333
16.5.7.226 QUEUE_47_D Register (offset = 22FCh) [reset = 0h]
2334
16.5.7.227 QUEUE_48_A Register (offset = 2300h) [reset = 0h]
2335
16.5.7.228 QUEUE_48_B Register (offset = 2304h) [reset = 0h]
2336
16.5.7.229 QUEUE_48_C Register (offset = 2308h) [reset = 0h]
2337
16.5.7.230 QUEUE_48_D Register (offset = 230Ch) [reset = 0h]
2338
16.5.7.231 QUEUE_49_A Register (offset = 2310h) [reset = 0h]
2339
16.5.7.232 QUEUE_49_B Register (offset = 2314h) [reset = 0h]
2340
16.5.7.233 QUEUE_49_C Register (offset = 2318h) [reset = 0h]
2341
16.5.7.234 QUEUE_49_D Register (offset = 231Ch) [reset = 0h]
2342
16.5.7.235 QUEUE_50_A Register (offset = 2320h) [reset = 0h]
2343
16.5.7.236 QUEUE_50_B Register (offset = 2324h) [reset = 0h]
2344
16.5.7.237 QUEUE_50_C Register (offset = 2328h) [reset = 0h]
2345
16.5.7.238 QUEUE_50_D Register (offset = 232Ch) [reset = 0h]
2346
16.5.7.239 QUEUE_51_A Register (offset = 2330h) [reset = 0h]
2347
16.5.7.240 QUEUE_51_B Register (offset = 2334h) [reset = 0h]
2348
16.5.7.241 QUEUE_51_C Register (offset = 2338h) [reset = 0h]
2349
16.5.7.242 QUEUE_51_D Register (offset = 233Ch) [reset = 0h]
2350
16.5.7.243 QUEUE_52_A Register (offset = 2340h) [reset = 0h]
2351
16.5.7.244 QUEUE_52_B Register (offset = 2344h) [reset = 0h]
2352
16.5.7.245 QUEUE_52_C Register (offset = 2348h) [reset = 0h]
2353
16.5.7.246 QUEUE_52_D Register (offset = 234Ch) [reset = 0h]
2354
16.5.7.247 QUEUE_53_A Register (offset = 2350h) [reset = 0h]
2355
16.5.7.248 QUEUE_53_B Register (offset = 2354h) [reset = 0h]
2356
16.5.7.249 QUEUE_53_C Register (offset = 2358h) [reset = 0h]
2357
16.5.7.250 QUEUE_53_D Register (offset = 235Ch) [reset = 0h]
2358
16.5.7.251 QUEUE_54_A Register (offset = 2360h) [reset = 0h]
2359
16.5.7.252 QUEUE_54_B Register (offset = 2364h) [reset = 0h]
2360
16.5.7.253 QUEUE_54_C Register (offset = 2368h) [reset = 0h]
2361
16.5.7.254 QUEUE_54_D Register (offset = 236Ch) [reset = 0h]
2362
16.5.7.255 QUEUE_55_A Register (offset = 2370h) [reset = 0h]
2363
16.5.7.256 QUEUE_55_B Register (offset = 2374h) [reset = 0h]
2364
16.5.7.257 QUEUE_55_C Register (offset = 2378h) [reset = 0h]
2365
16.5.7.258 QUEUE_55_D Register (offset = 237Ch) [reset = 0h]
2366
16.5.7.259 QUEUE_56_A Register (offset = 2380h) [reset = 0h]
2367
16.5.7.260 QUEUE_56_B Register (offset = 2384h) [reset = 0h]
2368
16.5.7.261 QUEUE_56_C Register (offset = 2388h) [reset = 0h]
2369
16.5.7.262 QUEUE_56_D Register (offset = 238Ch) [reset = 0h]
2370
16.5.7.263 QUEUE_57_A Register (offset = 2390h) [reset = 0h]
2371
16.5.7.264 QUEUE_57_B Register (offset = 2394h) [reset = 0h]
2372
16.5.7.265 QUEUE_57_C Register (offset = 2398h) [reset = 0h]
2373
16.5.7.266 QUEUE_57_D Register (offset = 239Ch) [reset = 0h]
2374
16.5.7.267 QUEUE_58_A Register (offset = 23A0h) [reset = 0h]
2375
16.5.7.268 QUEUE_58_B Register (offset = 23A4h) [reset = 0h]
2376
16.5.7.269 QUEUE_58_C Register (offset = 23A8h) [reset = 0h]
2377
16.5.7.270 QUEUE_58_D Register (offset = 23ACh) [reset = 0h]
2378
16.5.7.271 QUEUE_59_A Register (offset = 23B0h) [reset = 0h]
2379
16.5.7.272 QUEUE_59_B Register (offset = 23B4h) [reset = 0h]
2380
16.5.7.273 QUEUE_59_C Register (offset = 23B8h) [reset = 0h]
2381
16.5.7.274 QUEUE_59_D Register (offset = 23BCh) [reset = 0h]
2382
16.5.7.275 QUEUE_60_A Register (offset = 23C0h) [reset = 0h]
2383
16.5.7.276 QUEUE_60_B Register (offset = 23C4h) [reset = 0h]
2384
16.5.7.277 QUEUE_60_C Register (offset = 23C8h) [reset = 0h]
2385
16.5.7.278 QUEUE_60_D Register (offset = 23CCh) [reset = 0h]
2386
16.5.7.279 QUEUE_61_A Register (offset = 23D0h) [reset = 0h]
2387
16.5.7.280 QUEUE_61_B Register (offset = 23D4h) [reset = 0h]
2388
16.5.7.281 QUEUE_61_C Register (offset = 23D8h) [reset = 0h]
2389
16.5.7.282 QUEUE_61_D Register (offset = 23DCh) [reset = 0h]
2390
16.5.7.283 QUEUE_62_A Register (offset = 23E0h) [reset = 0h]
2391
16.5.7.284 QUEUE_62_B Register (offset = 23E4h) [reset = 0h]
2392
16.5.7.285 QUEUE_62_C Register (offset = 23E8h) [reset = 0h]
2393
16.5.7.286 QUEUE_62_D Register (offset = 23ECh) [reset = 0h]
2394
16.5.7.287 QUEUE_63_A Register (offset = 23F0h) [reset = 0h]
2395
16.5.7.288 QUEUE_63_B Register (offset = 23F4h) [reset = 0h]
2396
16.5.7.289 QUEUE_63_C Register (offset = 23F8h) [reset = 0h]
2397
16.5.7.290 QUEUE_63_D Register (offset = 23FCh) [reset = 0h]
2398
16.5.7.291 QUEUE_64_A Register (offset = 2400h) [reset = 0h]
2399
16.5.7.292 QUEUE_64_B Register (offset = 2404h) [reset = 0h]
2400
16.5.7.293 QUEUE_64_C Register (offset = 2408h) [reset = 0h]
2401
16.5.7.294 QUEUE_64_D Register (offset = 240Ch) [reset = 0h]
2402
16.5.7.295 QUEUE_65_A Register (offset = 2410h) [reset = 0h]
2403
16.5.7.296 QUEUE_65_B Register (offset = 2414h) [reset = 0h]
2404
16.5.7.297 QUEUE_65_C Register (offset = 2418h) [reset = 0h]
2405
16.5.7.298 QUEUE_65_D Register (offset = 241Ch) [reset = 0h]
2406
16.5.7.299 QUEUE_66_A Register (offset = 2420h) [reset = 0h]
2407
16.5.7.300 QUEUE_66_B Register (offset = 2424h) [reset = 0h]
2408
16.5.7.301 QUEUE_66_C Register (offset = 2428h) [reset = 0h]
2409
16.5.7.302 QUEUE_66_D Register (offset = 242Ch) [reset = 0h]
2410
16.5.7.303 QUEUE_67_A Register (offset = 2430h) [reset = 0h]
2411
16.5.7.304 QUEUE_67_B Register (offset = 2434h) [reset = 0h]
2412
16.5.7.305 QUEUE_67_C Register (offset = 2438h) [reset = 0h]
2413
16.5.7.306 QUEUE_67_D Register (offset = 243Ch) [reset = 0h]
2414
16.5.7.307 QUEUE_68_A Register (offset = 2440h) [reset = 0h]
2415
16.5.7.308 QUEUE_68_B Register (offset = 2444h) [reset = 0h]
2416
16.5.7.309 QUEUE_68_C Register (offset = 2448h) [reset = 0h]
2417
16.5.7.310 QUEUE_68_D Register (offset = 244Ch) [reset = 0h]
2418
16.5.7.311 QUEUE_69_A Register (offset = 2450h) [reset = 0h]
2419
16.5.7.312 QUEUE_69_B Register (offset = 2454h) [reset = 0h]
2420
16.5.7.313 QUEUE_69_C Register (offset = 2458h) [reset = 0h]
2421
16.5.7.314 QUEUE_69_D Register (offset = 245Ch) [reset = 0h]
2422
16.5.7.315 QUEUE_70_A Register (offset = 2460h) [reset = 0h]
2423
16.5.7.316 QUEUE_70_B Register (offset = 2464h) [reset = 0h]
2424
16.5.7.317 QUEUE_70_C Register (offset = 2468h) [reset = 0h]
2425
16.5.7.318 QUEUE_70_D Register (offset = 246Ch) [reset = 0h]
2426
16.5.7.319 QUEUE_71_A Register (offset = 2470h) [reset = 0h]
2427
16.5.7.320 QUEUE_71_B Register (offset = 2474h) [reset = 0h]
2428
16.5.7.321 QUEUE_71_C Register (offset = 2478h) [reset = 0h]
2429
16.5.7.322 QUEUE_71_D Register (offset = 247Ch) [reset = 0h]
2430
16.5.7.323 QUEUE_72_A Register (offset = 2480h) [reset = 0h]
2431
16.5.7.324 QUEUE_72_B Register (offset = 2484h) [reset = 0h]
2432
16.5.7.325 QUEUE_72_C Register (offset = 2488h) [reset = 0h]
2433
16.5.7.326 QUEUE_72_D Register (offset = 248Ch) [reset = 0h]
2434
16.5.7.327 QUEUE_73_A Register (offset = 2490h) [reset = 0h]
2435
16.5.7.328 QUEUE_73_B Register (offset = 2494h) [reset = 0h]
2436
16.5.7.329 QUEUE_73_C Register (offset = 2498h) [reset = 0h]
2437
16.5.7.330 QUEUE_73_D Register (offset = 249Ch) [reset = 0h]
2438
16.5.7.331 QUEUE_74_A Register (offset = 24A0h) [reset = 0h]
2439
16.5.7.332 QUEUE_74_B Register (offset = 24A4h) [reset = 0h]
2440
16.5.7.333 QUEUE_74_C Register (offset = 24A8h) [reset = 0h]
2441
16.5.7.334 QUEUE_74_D Register (offset = 24ACh) [reset = 0h]
2442
16.5.7.335 QUEUE_75_A Register (offset = 24B0h) [reset = 0h]
2443
16.5.7.336 QUEUE_75_B Register (offset = 24B4h) [reset = 0h]
2444
16.5.7.337 QUEUE_75_C Register (offset = 24B8h) [reset = 0h]
2445
16.5.7.338 QUEUE_75_D Register (offset = 24BCh) [reset = 0h]
2446
16.5.7.339 QUEUE_76_A Register (offset = 24C0h) [reset = 0h]
2447
16.5.7.340 QUEUE_76_B Register (offset = 24C4h) [reset = 0h]
2448
16.5.7.341 QUEUE_76_C Register (offset = 24C8h) [reset = 0h]
2449
16.5.7.342 QUEUE_76_D Register (offset = 24CCh) [reset = 0h]
2450
16.5.7.343 QUEUE_77_A Register (offset = 24D0h) [reset = 0h]
2451
16.5.7.344 QUEUE_77_B Register (offset = 24D4h) [reset = 0h]
2452
16.5.7.345 QUEUE_77_C Register (offset = 24D8h) [reset = 0h]
2453
16.5.7.346 QUEUE_77_D Register (offset = 24DCh) [reset = 0h]
2454
16.5.7.347 QUEUE_78_A Register (offset = 24E0h) [reset = 0h]
2455
16.5.7.348 QUEUE_78_B Register (offset = 24E4h) [reset = 0h]
2456
16.5.7.349 QUEUE_78_C Register (offset = 24E8h) [reset = 0h]
2457
16.5.7.350 QUEUE_78_D Register (offset = 24ECh) [reset = 0h]
2458
16.5.7.351 QUEUE_79_A Register (offset = 24F0h) [reset = 0h]
2459
16.5.7.352 QUEUE_79_B Register (offset = 24F4h) [reset = 0h]
2460
16.5.7.353 QUEUE_79_C Register (offset = 24F8h) [reset = 0h]
2461
16.5.7.354 QUEUE_79_D Register (offset = 24FCh) [reset = 0h]
2462
16.5.7.355 QUEUE_80_A Register (offset = 2500h) [reset = 0h]
2463
16.5.7.356 QUEUE_80_B Register (offset = 2504h) [reset = 0h]
2464
16.5.7.357 QUEUE_80_C Register (offset = 2508h) [reset = 0h]
2465
16.5.7.358 QUEUE_80_D Register (offset = 250Ch) [reset = 0h]
2466
16.5.7.359 QUEUE_81_A Register (offset = 2510h) [reset = 0h]
2467
16.5.7.360 QUEUE_81_B Register (offset = 2514h) [reset = 0h]
2468
16.5.7.361 QUEUE_81_C Register (offset = 2518h) [reset = 0h]
2469
16.5.7.362 QUEUE_81_D Register (offset = 251Ch) [reset = 0h]
2470
16.5.7.363 QUEUE_82_A Register (offset = 2520h) [reset = 0h]
2471
16.5.7.364 QUEUE_82_B Register (offset = 2524h) [reset = 0h]
2472
16.5.7.365 QUEUE_82_C Register (offset = 2528h) [reset = 0h]
2473
16.5.7.366 QUEUE_82_D Register (offset = 252Ch) [reset = 0h]
2474
16.5.7.367 QUEUE_83_A Register (offset = 2530h) [reset = 0h]
2475
16.5.7.368 QUEUE_83_B Register (offset = 2534h) [reset = 0h]
2476
16.5.7.369 QUEUE_83_C Register (offset = 2538h) [reset = 0h]
2477
16.5.7.370 QUEUE_83_D Register (offset = 253Ch) [reset = 0h]
2478
16.5.7.371 QUEUE_84_A Register (offset = 2540h) [reset = 0h]
2479
16.5.7.372 QUEUE_84_B Register (offset = 2544h) [reset = 0h]
2480
16.5.7.373 QUEUE_84_C Register (offset = 2548h) [reset = 0h]
2481
16.5.7.374 QUEUE_84_D Register (offset = 254Ch) [reset = 0h]
2482
16.5.7.375 QUEUE_85_A Register (offset = 2550h) [reset = 0h]
2483
16.5.7.376 QUEUE_85_B Register (offset = 2554h) [reset = 0h]
2484
16.5.7.377 QUEUE_85_C Register (offset = 2558h) [reset = 0h]
2485
16.5.7.378 QUEUE_85_D Register (offset = 255Ch) [reset = 0h]
2486
16.5.7.379 QUEUE_86_A Register (offset = 2560h) [reset = 0h]
2487
16.5.7.380 QUEUE_86_B Register (offset = 2564h) [reset = 0h]
2488
16.5.7.381 QUEUE_86_C Register (offset = 2568h) [reset = 0h]
2489
16.5.7.382 QUEUE_86_D Register (offset = 256Ch) [reset = 0h]
2490
16.5.7.383 QUEUE_87_A Register (offset = 2570h) [reset = 0h]
2491
16.5.7.384 QUEUE_87_B Register (offset = 2574h) [reset = 0h]
2492
16.5.7.385 QUEUE_87_C Register (offset = 2578h) [reset = 0h]
2493
16.5.7.386 QUEUE_87_D Register (offset = 257Ch) [reset = 0h]
2494
16.5.7.387 QUEUE_88_A Register (offset = 2580h) [reset = 0h]
2495
16.5.7.388 QUEUE_88_B Register (offset = 2584h) [reset = 0h]
2496
16.5.7.389 QUEUE_88_C Register (offset = 2588h) [reset = 0h]
2497
16.5.7.390 QUEUE_88_D Register (offset = 258Ch) [reset = 0h]
2498
16.5.7.391 QUEUE_89_A Register (offset = 2590h) [reset = 0h]
2499
16.5.7.392 QUEUE_89_B Register (offset = 2594h) [reset = 0h]
2500
16.5.7.393 QUEUE_89_C Register (offset = 2598h) [reset = 0h]
2501
16.5.7.394 QUEUE_89_D Register (offset = 259Ch) [reset = 0h]
2502
16.5.7.395 QUEUE_90_A Register (offset = 25A0h) [reset = 0h]
2503
16.5.7.396 QUEUE_90_B Register (offset = 25A4h) [reset = 0h]
2504
16.5.7.397 QUEUE_90_C Register (offset = 25A8h) [reset = 0h]
2505
16.5.7.398 QUEUE_90_D Register (offset = 25ACh) [reset = 0h]
2506
16.5.7.399 QUEUE_91_A Register (offset = 25B0h) [reset = 0h]
2507
16.5.7.400 QUEUE_91_B Register (offset = 25B4h) [reset = 0h]
2508
16.5.7.401 QUEUE_91_C Register (offset = 25B8h) [reset = 0h]
2509
16.5.7.402 QUEUE_91_D Register (offset = 25BCh) [reset = 0h]
2510
16.5.7.403 QUEUE_92_A Register (offset = 25C0h) [reset = 0h]
2511
16.5.7.404 QUEUE_92_B Register (offset = 25C4h) [reset = 0h]
2512
16.5.7.405 QUEUE_92_C Register (offset = 25C8h) [reset = 0h]
2513
16.5.7.406 QUEUE_92_D Register (offset = 25CCh) [reset = 0h]
2514
16.5.7.407 QUEUE_93_A Register (offset = 25D0h) [reset = 0h]
2515
16.5.7.408 QUEUE_93_B Register (offset = 25D4h) [reset = 0h]
2516
16.5.7.409 QUEUE_93_C Register (offset = 25D8h) [reset = 0h]
2517
16.5.7.410 QUEUE_93_D Register (offset = 25DCh) [reset = 0h]
2518
16.5.7.411 QUEUE_94_A Register (offset = 25E0h) [reset = 0h]
2519
16.5.7.412 QUEUE_94_B Register (offset = 25E4h) [reset = 0h]
2520
16.5.7.413 QUEUE_94_C Register (offset = 25E8h) [reset = 0h]
2521
16.5.7.414 QUEUE_94_D Register (offset = 25ECh) [reset = 0h]
2522
16.5.7.415 QUEUE_95_A Register (offset = 25F0h) [reset = 0h]
2523
16.5.7.416 QUEUE_95_B Register (offset = 25F4h) [reset = 0h]
2524
16.5.7.417 QUEUE_95_C Register (offset = 25F8h) [reset = 0h]
2525
16.5.7.418 QUEUE_95_D Register (offset = 25FCh) [reset = 0h]
2526
16.5.7.419 QUEUE_96_A Register (offset = 2600h) [reset = 0h]
2527
16.5.7.420 QUEUE_96_B Register (offset = 2604h) [reset = 0h]
2528
16.5.7.421 QUEUE_96_C Register (offset = 2608h) [reset = 0h]
2529
16.5.7.422 QUEUE_96_D Register (offset = 260Ch) [reset = 0h]
2530
16.5.7.423 QUEUE_97_A Register (offset = 2610h) [reset = 0h]
2531
16.5.7.424 QUEUE_97_B Register (offset = 2614h) [reset = 0h]
2532
16.5.7.425 QUEUE_97_C Register (offset = 2618h) [reset = 0h]
2533
16.5.7.426 QUEUE_97_D Register (offset = 261Ch) [reset = 0h]
2534
16.5.7.427 QUEUE_98_A Register (offset = 2620h) [reset = 0h]
2535
16.5.7.428 QUEUE_98_B Register (offset = 2624h) [reset = 0h]
2536
16.5.7.429 QUEUE_98_C Register (offset = 2628h) [reset = 0h]
2537
16.5.7.430 QUEUE_98_D Register (offset = 262Ch) [reset = 0h]
2538
16.5.7.431 QUEUE_99_A Register (offset = 2630h) [reset = 0h]
2539
16.5.7.432 QUEUE_99_B Register (offset = 2634h) [reset = 0h]
2540
16.5.7.433 QUEUE_99_C Register (offset = 2638h) [reset = 0h]
2541
16.5.7.434 QUEUE_99_D Register (offset = 263Ch) [reset = 0h]
2542
16.5.7.435 QUEUE_100_A Register (offset = 2640h) [reset = 0h]
2543
16.5.7.436 QUEUE_100_B Register (offset = 2644h) [reset = 0h]
2544
16.5.7.437 QUEUE_100_C Register (offset = 2648h) [reset = 0h]
2545
16.5.7.438 QUEUE_100_D Register (offset = 264Ch) [reset = 0h]
2546
16.5.7.439 QUEUE_101_A Register (offset = 2650h) [reset = 0h]
2547
16.5.7.440 QUEUE_101_B Register (offset = 2654h) [reset = 0h]
2548
16.5.7.441 QUEUE_101_C Register (offset = 2658h) [reset = 0h]
2549
16.5.7.442 QUEUE_101_D Register (offset = 265Ch) [reset = 0h]
2550
16.5.7.443 QUEUE_102_A Register (offset = 2660h) [reset = 0h]
2551
16.5.7.444 QUEUE_102_B Register (offset = 2664h) [reset = 0h]
2552
16.5.7.445 QUEUE_102_C Register (offset = 2668h) [reset = 0h]
2553
16.5.7.446 QUEUE_102_D Register (offset = 266Ch) [reset = 0h]
2554
16.5.7.447 QUEUE_103_A Register (offset = 2670h) [reset = 0h]
2555
16.5.7.448 QUEUE_103_B Register (offset = 2674h) [reset = 0h]
2556
16.5.7.449 QUEUE_103_C Register (offset = 2678h) [reset = 0h]
2557
16.5.7.450 QUEUE_103_D Register (offset = 267Ch) [reset = 0h]
2558
16.5.7.451 QUEUE_104_A Register (offset = 2680h) [reset = 0h]
2559
16.5.7.452 QUEUE_104_B Register (offset = 2684h) [reset = 0h]
2560
16.5.7.453 QUEUE_104_C Register (offset = 2688h) [reset = 0h]
2561
16.5.7.454 QUEUE_104_D Register (offset = 268Ch) [reset = 0h]
2562
16.5.7.455 QUEUE_105_A Register (offset = 2690h) [reset = 0h]
2563
16.5.7.456 QUEUE_105_B Register (offset = 2694h) [reset = 0h]
2564
16.5.7.457 QUEUE_105_C Register (offset = 2698h) [reset = 0h]
2565
16.5.7.458 QUEUE_105_D Register (offset = 269Ch) [reset = 0h]
2566
16.5.7.459 QUEUE_106_A Register (offset = 26A0h) [reset = 0h]
2567
16.5.7.460 QUEUE_106_B Register (offset = 26A4h) [reset = 0h]
2568
16.5.7.461 QUEUE_106_C Register (offset = 26A8h) [reset = 0h]
2569
16.5.7.462 QUEUE_106_D Register (offset = 26ACh) [reset = 0h]
2570
16.5.7.463 QUEUE_107_A Register (offset = 26B0h) [reset = 0h]
2571
16.5.7.464 QUEUE_107_B Register (offset = 26B4h) [reset = 0h]
2572
16.5.7.465 QUEUE_107_C Register (offset = 26B8h) [reset = 0h]
2573
16.5.7.466 QUEUE_107_D Register (offset = 26BCh) [reset = 0h]
2574
16.5.7.467 QUEUE_108_A Register (offset = 26C0h) [reset = 0h]
2575
16.5.7.468 QUEUE_108_B Register (offset = 26C4h) [reset = 0h]
2576
16.5.7.469 QUEUE_108_C Register (offset = 26C8h) [reset = 0h]
2577
16.5.7.470 QUEUE_108_D Register (offset = 26CCh) [reset = 0h]
2578
16.5.7.471 QUEUE_109_A Register (offset = 26D0h) [reset = 0h]
2579
16.5.7.472 QUEUE_109_B Register (offset = 26D4h) [reset = 0h]
2580
16.5.7.473 QUEUE_109_C Register (offset = 26D8h) [reset = 0h]
2581
16.5.7.474 QUEUE_109_D Register (offset = 26DCh) [reset = 0h]
2582
16.5.7.475 QUEUE_110_A Register (offset = 26E0h) [reset = 0h]
2583
16.5.7.476 QUEUE_110_B Register (offset = 26E4h) [reset = 0h]
2584
16.5.7.477 QUEUE_110_C Register (offset = 26E8h) [reset = 0h]
2585
16.5.7.478 QUEUE_110_D Register (offset = 26ECh) [reset = 0h]
2586
16.5.7.479 QUEUE_111_A Register (offset = 26F0h) [reset = 0h]
2587
16.5.7.480 QUEUE_111_B Register (offset = 26F4h) [reset = 0h]
2588
16.5.7.481 QUEUE_111_C Register (offset = 26F8h) [reset = 0h]
2589
16.5.7.482 QUEUE_111_D Register (offset = 26FCh) [reset = 0h]
2590
16.5.7.483 QUEUE_112_A Register (offset = 2700h) [reset = 0h]
2591
16.5.7.484 QUEUE_112_B Register (offset = 2704h) [reset = 0h]
2592
16.5.7.485 QUEUE_112_C Register (offset = 2708h) [reset = 0h]
2593
16.5.7.486 QUEUE_112_D Register (offset = 270Ch) [reset = 0h]
2594
16.5.7.487 QUEUE_113_A Register (offset = 2710h) [reset = 0h]
2595
16.5.7.488 QUEUE_113_B Register (offset = 2714h) [reset = 0h]
2596
16.5.7.489 QUEUE_113_C Register (offset = 2718h) [reset = 0h]
2597
16.5.7.490 QUEUE_113_D Register (offset = 271Ch) [reset = 0h]
2598
16.5.7.491 QUEUE_114_A Register (offset = 2720h) [reset = 0h]
2599
16.5.7.492 QUEUE_114_B Register (offset = 2724h) [reset = 0h]
2600
16.5.7.493 QUEUE_114_C Register (offset = 2728h) [reset = 0h]
2601
16.5.7.494 QUEUE_114_D Register (offset = 272Ch) [reset = 0h]
2602
16.5.7.495 QUEUE_115_A Register (offset = 2730h) [reset = 0h]
2603
16.5.7.496 QUEUE_115_B Register (offset = 2734h) [reset = 0h]
2604
16.5.7.497 QUEUE_115_C Register (offset = 2738h) [reset = 0h]
2605
16.5.7.498 QUEUE_115_D Register (offset = 273Ch) [reset = 0h]
2606
16.5.7.499 QUEUE_116_A Register (offset = 2740h) [reset = 0h]
2607
16.5.7.500 QUEUE_116_B Register (offset = 2744h) [reset = 0h]
2608
16.5.7.501 QUEUE_116_C Register (offset = 2748h) [reset = 0h]
2609
16.5.7.502 QUEUE_116_D Register (offset = 274Ch) [reset = 0h]
2610
16.5.7.503 QUEUE_117_A Register (offset = 2750h) [reset = 0h]
2611
16.5.7.504 QUEUE_117_B Register (offset = 2754h) [reset = 0h]
2612
16.5.7.505 QUEUE_117_C Register (offset = 2758h) [reset = 0h]
2613
16.5.7.506 QUEUE_117_D Register (offset = 275Ch) [reset = 0h]
2614
16.5.7.507 QUEUE_118_A Register (offset = 2760h) [reset = 0h]
2615
16.5.7.508 QUEUE_118_B Register (offset = 2764h) [reset = 0h]
2616
16.5.7.509 QUEUE_118_C Register (offset = 2768h) [reset = 0h]
2617
16.5.7.510 QUEUE_118_D Register (offset = 276Ch) [reset = 0h]
2618
16.5.7.511 QUEUE_119_A Register (offset = 2770h) [reset = 0h]
2619
16.5.7.512 QUEUE_119_B Register (offset = 2774h) [reset = 0h]
2620
16.5.7.513 QUEUE_119_C Register (offset = 2778h) [reset = 0h]
2621
16.5.7.514 QUEUE_119_D Register (offset = 277Ch) [reset = 0h]
2622
16.5.7.515 QUEUE_120_A Register (offset = 2780h) [reset = 0h]
2623
16.5.7.516 QUEUE_120_B Register (offset = 2784h) [reset = 0h]
2624
16.5.7.517 QUEUE_120_C Register (offset = 2788h) [reset = 0h]
2625
16.5.7.518 QUEUE_120_D Register (offset = 278Ch) [reset = 0h]
2626
16.5.7.519 QUEUE_121_A Register (offset = 2790h) [reset = 0h]
2627
16.5.7.520 QUEUE_121_B Register (offset = 2794h) [reset = 0h]
2628
16.5.7.521 QUEUE_121_C Register (offset = 2798h) [reset = 0h]
2629
16.5.7.522 QUEUE_121_D Register (offset = 279Ch) [reset = 0h]
2630
16.5.7.523 QUEUE_122_A Register (offset = 27A0h) [reset = 0h]
2631
16.5.7.524 QUEUE_122_B Register (offset = 27A4h) [reset = 0h]
2632
16.5.7.525 QUEUE_122_C Register (offset = 27A8h) [reset = 0h]
2633
16.5.7.526 QUEUE_122_D Register (offset = 27ACh) [reset = 0h]
2634
16.5.7.527 QUEUE_123_A Register (offset = 27B0h) [reset = 0h]
2635
16.5.7.528 QUEUE_123_B Register (offset = 27B4h) [reset = 0h]
2636
16.5.7.529 QUEUE_123_C Register (offset = 27B8h) [reset = 0h]
2637
16.5.7.530 QUEUE_123_D Register (offset = 27BCh) [reset = 0h]
2638
16.5.7.531 QUEUE_124_A Register (offset = 27C0h) [reset = 0h]
2639
16.5.7.532 QUEUE_124_B Register (offset = 27C4h) [reset = 0h]
2640
16.5.7.533 QUEUE_124_C Register (offset = 27C8h) [reset = 0h]
2641
16.5.7.534 QUEUE_124_D Register (offset = 27CCh) [reset = 0h]
2642
16.5.7.535 QUEUE_125_A Register (offset = 27D0h) [reset = 0h]
2643
16.5.7.536 QUEUE_125_B Register (offset = 27D4h) [reset = 0h]
2644
16.5.7.537 QUEUE_125_C Register (offset = 27D8h) [reset = 0h]
2645
16.5.7.538 QUEUE_125_D Register (offset = 27DCh) [reset = 0h]
2646
16.5.7.539 QUEUE_126_A Register (offset = 27E0h) [reset = 0h]
2647
16.5.7.540 QUEUE_126_B Register (offset = 27E4h) [reset = 0h]
2648
16.5.7.541 QUEUE_126_C Register (offset = 27E8h) [reset = 0h]
2649
16.5.7.542 QUEUE_126_D Register (offset = 27ECh) [reset = 0h]
2650
16.5.7.543 QUEUE_127_A Register (offset = 27F0h) [reset = 0h]
2651
16.5.7.544 QUEUE_127_B Register (offset = 27F4h) [reset = 0h]
2652
16.5.7.545 QUEUE_127_C Register (offset = 27F8h) [reset = 0h]
2653
16.5.7.546 QUEUE_127_D Register (offset = 27FCh) [reset = 0h]
2654
16.5.7.547 QUEUE_128_A Register (offset = 2800h) [reset = 0h]
2655
16.5.7.548 QUEUE_128_B Register (offset = 2804h) [reset = 0h]
2656
16.5.7.549 QUEUE_128_C Register (offset = 2808h) [reset = 0h]
2657
16.5.7.550 QUEUE_128_D Register (offset = 280Ch) [reset = 0h]
2658
16.5.7.551 QUEUE_129_A Register (offset = 2810h) [reset = 0h]
2659
16.5.7.552 QUEUE_129_B Register (offset = 2814h) [reset = 0h]
2660
16.5.7.553 QUEUE_129_C Register (offset = 2818h) [reset = 0h]
2661
16.5.7.554 QUEUE_129_D Register (offset = 281Ch) [reset = 0h]
2662
16.5.7.555 QUEUE_130_A Register (offset = 2820h) [reset = 0h]
2663
16.5.7.556 QUEUE_130_B Register (offset = 2824h) [reset = 0h]
2664
16.5.7.557 QUEUE_130_C Register (offset = 2828h) [reset = 0h]
2665
16.5.7.558 QUEUE_130_D Register (offset = 282Ch) [reset = 0h]
2666
16.5.7.559 QUEUE_131_A Register (offset = 2830h) [reset = 0h]
2667
16.5.7.560 QUEUE_131_B Register (offset = 2834h) [reset = 0h]
2668
16.5.7.561 QUEUE_131_C Register (offset = 2838h) [reset = 0h]
2669
16.5.7.562 QUEUE_131_D Register (offset = 283Ch) [reset = 0h]
2670
16.5.7.563 QUEUE_132_A Register (offset = 2840h) [reset = 0h]
2671
16.5.7.564 QUEUE_132_B Register (offset = 2844h) [reset = 0h]
2672
16.5.7.565 QUEUE_132_C Register (offset = 2848h) [reset = 0h]
2673
16.5.7.566 QUEUE_132_D Register (offset = 284Ch) [reset = 0h]
2674
16.5.7.567 QUEUE_133_A Register (offset = 2850h) [reset = 0h]
2675
16.5.7.568 QUEUE_133_B Register (offset = 2854h) [reset = 0h]
2676
16.5.7.569 QUEUE_133_C Register (offset = 2858h) [reset = 0h]
2677
16.5.7.570 QUEUE_133_D Register (offset = 285Ch) [reset = 0h]
2678
16.5.7.571 QUEUE_134_A Register (offset = 2860h) [reset = 0h]
2679
16.5.7.572 QUEUE_134_B Register (offset = 2864h) [reset = 0h]
2680
16.5.7.573 QUEUE_134_C Register (offset = 2868h) [reset = 0h]
2681
16.5.7.574 QUEUE_134_D Register (offset = 286Ch) [reset = 0h]
2682
16.5.7.575 QUEUE_135_A Register (offset = 2870h) [reset = 0h]
2683
16.5.7.576 QUEUE_135_B Register (offset = 2874h) [reset = 0h]
2684
16.5.7.577 QUEUE_135_C Register (offset = 2878h) [reset = 0h]
2685
16.5.7.578 QUEUE_135_D Register (offset = 287Ch) [reset = 0h]
2686
16.5.7.579 QUEUE_136_A Register (offset = 2880h) [reset = 0h]
2687
16.5.7.580 QUEUE_136_B Register (offset = 2884h) [reset = 0h]
2688
16.5.7.581 QUEUE_136_C Register (offset = 2888h) [reset = 0h]
2689
16.5.7.582 QUEUE_136_D Register (offset = 288Ch) [reset = 0h]
2690
16.5.7.583 QUEUE_137_A Register (offset = 2890h) [reset = 0h]
2691
16.5.7.584 QUEUE_137_B Register (offset = 2894h) [reset = 0h]
2692
16.5.7.585 QUEUE_137_C Register (offset = 2898h) [reset = 0h]
2693
16.5.7.586 QUEUE_137_D Register (offset = 289Ch) [reset = 0h]
2694
16.5.7.587 QUEUE_138_A Register (offset = 28A0h) [reset = 0h]
2695
16.5.7.588 QUEUE_138_B Register (offset = 28A4h) [reset = 0h]
2696
16.5.7.589 QUEUE_138_C Register (offset = 28A8h) [reset = 0h]
2697
16.5.7.590 QUEUE_138_D Register (offset = 28ACh) [reset = 0h]
2698
16.5.7.591 QUEUE_139_A Register (offset = 28B0h) [reset = 0h]
2699
16.5.7.592 QUEUE_139_B Register (offset = 28B4h) [reset = 0h]
2700
16.5.7.593 QUEUE_139_C Register (offset = 28B8h) [reset = 0h]
2701
16.5.7.594 QUEUE_139_D Register (offset = 28BCh) [reset = 0h]
2702
16.5.7.595 QUEUE_140_A Register (offset = 28C0h) [reset = 0h]
2703
16.5.7.596 QUEUE_140_B Register (offset = 28C4h) [reset = 0h]
2704
16.5.7.597 QUEUE_140_C Register (offset = 28C8h) [reset = 0h]
2705
16.5.7.598 QUEUE_140_D Register (offset = 28CCh) [reset = 0h]
2706
16.5.7.599 QUEUE_141_A Register (offset = 28D0h) [reset = 0h]
2707
16.5.7.600 QUEUE_141_B Register (offset = 28D4h) [reset = 0h]
2708
16.5.7.601 QUEUE_141_C Register (offset = 28D8h) [reset = 0h]
2709
16.5.7.602 QUEUE_141_D Register (offset = 28DCh) [reset = 0h]
2710
16.5.7.603 QUEUE_142_A Register (offset = 28E0h) [reset = 0h]
2711
16.5.7.604 QUEUE_142_B Register (offset = 28E4h) [reset = 0h]
2712
16.5.7.605 QUEUE_142_C Register (offset = 28E8h) [reset = 0h]
2713
16.5.7.606 QUEUE_142_D Register (offset = 28ECh) [reset = 0h]
2714
16.5.7.607 QUEUE_143_A Register (offset = 28F0h) [reset = 0h]
2715
16.5.7.608 QUEUE_143_B Register (offset = 28F4h) [reset = 0h]
2716
16.5.7.609 QUEUE_143_C Register (offset = 28F8h) [reset = 0h]
2717
16.5.7.610 QUEUE_143_D Register (offset = 28FCh) [reset = 0h]
2718
16.5.7.611 QUEUE_144_A Register (offset = 2900h) [reset = 0h]
2719
16.5.7.612 QUEUE_144_B Register (offset = 2904h) [reset = 0h]
2720
16.5.7.613 QUEUE_144_C Register (offset = 2908h) [reset = 0h]
2721
16.5.7.614 QUEUE_144_D Register (offset = 290Ch) [reset = 0h]
2722
16.5.7.615 QUEUE_145_A Register (offset = 2910h) [reset = 0h]
2723
16.5.7.616 QUEUE_145_B Register (offset = 2914h) [reset = 0h]
2724
16.5.7.617 QUEUE_145_C Register (offset = 2918h) [reset = 0h]
2725
16.5.7.618 QUEUE_145_D Register (offset = 291Ch) [reset = 0h]
2726
16.5.7.619 QUEUE_146_A Register (offset = 2920h) [reset = 0h]
2727
16.5.7.620 QUEUE_146_B Register (offset = 2924h) [reset = 0h]
2728
16.5.7.621 QUEUE_146_C Register (offset = 2928h) [reset = 0h]
2729
16.5.7.622 QUEUE_146_D Register (offset = 292Ch) [reset = 0h]
2730
16.5.7.623 QUEUE_147_A Register (offset = 2930h) [reset = 0h]
2731
16.5.7.624 QUEUE_147_B Register (offset = 2934h) [reset = 0h]
2732
16.5.7.625 QUEUE_147_C Register (offset = 2938h) [reset = 0h]
2733
16.5.7.626 QUEUE_147_D Register (offset = 293Ch) [reset = 0h]
2734
16.5.7.627 QUEUE_148_A Register (offset = 2940h) [reset = 0h]
2735
16.5.7.628 QUEUE_148_B Register (offset = 2944h) [reset = 0h]
2736
16.5.7.629 QUEUE_148_C Register (offset = 2948h) [reset = 0h]
2737
16.5.7.630 QUEUE_148_D Register (offset = 294Ch) [reset = 0h]
2738
16.5.7.631 QUEUE_149_A Register (offset = 2950h) [reset = 0h]
2739
16.5.7.632 QUEUE_149_B Register (offset = 2954h) [reset = 0h]
2740
16.5.7.633 QUEUE_149_C Register (offset = 2958h) [reset = 0h]
2741
16.5.7.634 QUEUE_149_D Register (offset = 295Ch) [reset = 0h]
2742
16.5.7.635 QUEUE_150_A Register (offset = 2960h) [reset = 0h]
2743
16.5.7.636 QUEUE_150_B Register (offset = 2964h) [reset = 0h]
2744
16.5.7.637 QUEUE_150_C Register (offset = 2968h) [reset = 0h]
2745
16.5.7.638 QUEUE_150_D Register (offset = 296Ch) [reset = 0h]
2746
16.5.7.639 QUEUE_151_A Register (offset = 2970h) [reset = 0h]
2747
16.5.7.640 QUEUE_151_B Register (offset = 2974h) [reset = 0h]
2748
16.5.7.641 QUEUE_151_C Register (offset = 2978h) [reset = 0h]
2749
16.5.7.642 QUEUE_151_D Register (offset = 297Ch) [reset = 0h]
2750
16.5.7.643 QUEUE_152_A Register (offset = 2980h) [reset = 0h]
2751
16.5.7.644 QUEUE_152_B Register (offset = 2984h) [reset = 0h]
2752
16.5.7.645 QUEUE_152_C Register (offset = 2988h) [reset = 0h]
2753
16.5.7.646 QUEUE_152_D Register (offset = 298Ch) [reset = 0h]
2754
16.5.7.647 QUEUE_153_A Register (offset = 2990h) [reset = 0h]
2755
16.5.7.648 QUEUE_153_B Register (offset = 2994h) [reset = 0h]
2756
16.5.7.649 QUEUE_153_C Register (offset = 2998h) [reset = 0h]
2757
16.5.7.650 QUEUE_153_D Register (offset = 299Ch) [reset = 0h]
2758
16.5.7.651 QUEUE_154_A Register (offset = 29A0h) [reset = 0h]
2759
16.5.7.652 QUEUE_154_B Register (offset = 29A4h) [reset = 0h]
2760
16.5.7.653 QUEUE_154_C Register (offset = 29A8h) [reset = 0h]
2761
16.5.7.654 QUEUE_154_D Register (offset = 29ACh) [reset = 0h]
2762
16.5.7.655 QUEUE_155_A Register (offset = 29B0h) [reset = 0h]
2763
16.5.7.656 QUEUE_155_B Register (offset = 29B4h) [reset = 0h]
2764
16.5.7.657 QUEUE_155_C Register (offset = 29B8h) [reset = 0h]
2765
16.5.7.658 QUEUE_155_D Register (offset = 29BCh) [reset = 0h]
2766
16.5.7.659 QUEUE_0_STATUS_A Register (offset = 3000h) [reset = 0h]
2767
16.5.7.660 QUEUE_0_STATUS_B Register (offset = 3004h) [reset = 0h]
2768
16.5.7.661 QUEUE_0_STATUS_C Register (offset = 3008h) [reset = 0h]
2769
16.5.7.662 QUEUE_1_STATUS_A Register (offset = 3010h) [reset = 0h]
2770
16.5.7.663 QUEUE_1_STATUS_B Register (offset = 3014h) [reset = 0h]
2771
16.5.7.664 QUEUE_1_STATUS_C Register (offset = 3018h) [reset = 0h]
2772
16.5.7.665 QUEUE_2_STATUS_A Register (offset = 3020h) [reset = 0h]
2773
16.5.7.666 QUEUE_2_STATUS_B Register (offset = 3024h) [reset = 0h]
2774
16.5.7.667 QUEUE_2_STATUS_C Register (offset = 3028h) [reset = 0h]
2775
16.5.7.668 QUEUE_3_STATUS_A Register (offset = 3030h) [reset = 0h]
2776
16.5.7.669 QUEUE_3_STATUS_B Register (offset = 3034h) [reset = 0h]
2777
16.5.7.670 QUEUE_3_STATUS_C Register (offset = 3038h) [reset = 0h]
2778
16.5.7.671 QUEUE_4_STATUS_A Register (offset = 3040h) [reset = 0h]
2779
16.5.7.672 QUEUE_4_STATUS_B Register (offset = 3044h) [reset = 0h]
2780
16.5.7.673 QUEUE_4_STATUS_C Register (offset = 3048h) [reset = 0h]
2781
16.5.7.674 QUEUE_5_STATUS_A Register (offset = 3050h) [reset = 0h]
2782
16.5.7.675 QUEUE_5_STATUS_B Register (offset = 3054h) [reset = 0h]
2783
16.5.7.676 QUEUE_5_STATUS_C Register (offset = 3058h) [reset = 0h]
2784
16.5.7.677 QUEUE_6_STATUS_A Register (offset = 3060h) [reset = 0h]
2785
16.5.7.678 QUEUE_6_STATUS_B Register (offset = 3064h) [reset = 0h]
2786
16.5.7.679 QUEUE_6_STATUS_C Register (offset = 3068h) [reset = 0h]
2787
16.5.7.680 QUEUE_7_STATUS_A Register (offset = 3070h) [reset = 0h]
2788
16.5.7.681 QUEUE_7_STATUS_B Register (offset = 3074h) [reset = 0h]
2789
16.5.7.682 QUEUE_7_STATUS_C Register (offset = 3078h) [reset = 0h]
2790
16.5.7.683 QUEUE_8_STATUS_A Register (offset = 3080h) [reset = 0h]
2791
16.5.7.684 QUEUE_8_STATUS_B Register (offset = 3084h) [reset = 0h]
2792
16.5.7.685 QUEUE_8_STATUS_C Register (offset = 3088h) [reset = 0h]
2793
16.5.7.686 QUEUE_9_STATUS_A Register (offset = 3090h) [reset = 0h]
2794
16.5.7.687 QUEUE_9_STATUS_B Register (offset = 3094h) [reset = 0h]
2795
16.5.7.688 QUEUE_9_STATUS_C Register (offset = 3098h) [reset = 0h]
2796
16.5.7.689 QUEUE_10_STATUS_A Register (offset = 30A0h) [reset = 0h]
2797
16.5.7.690 QUEUE_10_STATUS_B Register (offset = 30A4h) [reset = 0h]
2798
16.5.7.691 QUEUE_10_STATUS_C Register (offset = 30A8h) [reset = 0h]
2799
16.5.7.692 QUEUE_11_STATUS_A Register (offset = 30B0h) [reset = 0h]
2800
16.5.7.693 QUEUE_11_STATUS_B Register (offset = 30B4h) [reset = 0h]
2801
16.5.7.694 QUEUE_11_STATUS_C Register (offset = 30B8h) [reset = 0h]
2802
16.5.7.695 QUEUE_12_STATUS_A Register (offset = 30C0h) [reset = 0h]
2803
16.5.7.696 QUEUE_12_STATUS_B Register (offset = 30C4h) [reset = 0h]
2804
16.5.7.697 QUEUE_12_STATUS_C Register (offset = 30C8h) [reset = 0h]
2805
16.5.7.698 QUEUE_13_STATUS_A Register (offset = 30D0h) [reset = 0h]
2806
16.5.7.699 QUEUE_13_STATUS_B Register (offset = 30D4h) [reset = 0h]
2807
16.5.7.700 QUEUE_13_STATUS_C Register (offset = 30D8h) [reset = 0h]
2808
16.5.7.701 QUEUE_14_STATUS_A Register (offset = 30E0h) [reset = 0h]
2809
16.5.7.702 QUEUE_14_STATUS_B Register (offset = 30E4h) [reset = 0h]
2810
16.5.7.703 QUEUE_14_STATUS_C Register (offset = 30E8h) [reset = 0h]
2811
16.5.7.704 QUEUE_15_STATUS_A Register (offset = 30F0h) [reset = 0h]
2812
16.5.7.705 QUEUE_15_STATUS_B Register (offset = 30F4h) [reset = 0h]
2813
16.5.7.706 QUEUE_15_STATUS_C Register (offset = 30F8h) [reset = 0h]
2814
16.5.7.707 QUEUE_16_STATUS_A Register (offset = 3100h) [reset = 0h]
2815
16.5.7.708 QUEUE_16_STATUS_B Register (offset = 3104h) [reset = 0h]
2816
16.5.7.709 QUEUE_16_STATUS_C Register (offset = 3108h) [reset = 0h]
2817
16.5.7.710 QUEUE_17_STATUS_A Register (offset = 3110h) [reset = 0h]
2818
16.5.7.711 QUEUE_17_STATUS_B Register (offset = 3114h) [reset = 0h]
2819
16.5.7.712 QUEUE_17_STATUS_C Register (offset = 3118h) [reset = 0h]
2820
16.5.7.713 QUEUE_18_STATUS_A Register (offset = 3120h) [reset = 0h]
2821
16.5.7.714 QUEUE_18_STATUS_B Register (offset = 3124h) [reset = 0h]
2822
16.5.7.715 QUEUE_18_STATUS_C Register (offset = 3128h) [reset = 0h]
2823
16.5.7.716 QUEUE_19_STATUS_A Register (offset = 3130h) [reset = 0h]
2824
16.5.7.717 QUEUE_19_STATUS_B Register (offset = 3134h) [reset = 0h]
2825
16.5.7.718 QUEUE_19_STATUS_C Register (offset = 3138h) [reset = 0h]
2826
16.5.7.719 QUEUE_20_STATUS_A Register (offset = 3140h) [reset = 0h]
2827
16.5.7.720 QUEUE_20_STATUS_B Register (offset = 3144h) [reset = 0h]
2828
16.5.7.721 QUEUE_20_STATUS_C Register (offset = 3148h) [reset = 0h]
2829
16.5.7.722 QUEUE_21_STATUS_A Register (offset = 3150h) [reset = 0h]
2830
16.5.7.723 QUEUE_21_STATUS_B Register (offset = 3154h) [reset = 0h]
2831
16.5.7.724 QUEUE_21_STATUS_C Register (offset = 3158h) [reset = 0h]
2832
16.5.7.725 QUEUE_22_STATUS_A Register (offset = 3160h) [reset = 0h]
2833
16.5.7.726 QUEUE_22_STATUS_B Register (offset = 3164h) [reset = 0h]
2834
16.5.7.727 QUEUE_22_STATUS_C Register (offset = 3168h) [reset = 0h]
2835
16.5.7.728 QUEUE_23_STATUS_A Register (offset = 3170h) [reset = 0h]
2836
16.5.7.729 QUEUE_23_STATUS_B Register (offset = 3174h) [reset = 0h]
2837
16.5.7.730 QUEUE_23_STATUS_C Register (offset = 3178h) [reset = 0h]
2838
16.5.7.731 QUEUE_24_STATUS_A Register (offset = 3180h) [reset = 0h]
2839
16.5.7.732 QUEUE_24_STATUS_B Register (offset = 3184h) [reset = 0h]
2840
16.5.7.733 QUEUE_24_STATUS_C Register (offset = 3188h) [reset = 0h]
2841
16.5.7.734 QUEUE_25_STATUS_A Register (offset = 3190h) [reset = 0h]
2842
16.5.7.735 QUEUE_25_STATUS_B Register (offset = 3194h) [reset = 0h]
2843
16.5.7.736 QUEUE_25_STATUS_C Register (offset = 3198h) [reset = 0h]
2844
16.5.7.737 QUEUE_26_STATUS_A Register (offset = 31A0h) [reset = 0h]
2845
16.5.7.738 QUEUE_26_STATUS_B Register (offset = 31A4h) [reset = 0h]
2846
16.5.7.739 QUEUE_26_STATUS_C Register (offset = 31A8h) [reset = 0h]
2847
16.5.7.740 QUEUE_27_STATUS_A Register (offset = 31B0h) [reset = 0h]
2848
16.5.7.741 QUEUE_27_STATUS_B Register (offset = 31B4h) [reset = 0h]
2849
16.5.7.742 QUEUE_27_STATUS_C Register (offset = 31B8h) [reset = 0h]
2850
16.5.7.743 QUEUE_28_STATUS_A Register (offset = 31C0h) [reset = 0h]
2851
16.5.7.744 QUEUE_28_STATUS_B Register (offset = 31C4h) [reset = 0h]
2852
16.5.7.745 QUEUE_28_STATUS_C Register (offset = 31C8h) [reset = 0h]
2853
16.5.7.746 QUEUE_29_STATUS_A Register (offset = 31D0h) [reset = 0h]
2854
16.5.7.747 QUEUE_29_STATUS_B Register (offset = 31D4h) [reset = 0h]
2855
16.5.7.748 QUEUE_29_STATUS_C Register (offset = 31D8h) [reset = 0h]
2856
16.5.7.749 QUEUE_30_STATUS_A Register (offset = 31E0h) [reset = 0h]
2857
16.5.7.750 QUEUE_30_STATUS_B Register (offset = 31E4h) [reset = 0h]
2858
16.5.7.751 QUEUE_30_STATUS_C Register (offset = 31E8h) [reset = 0h]
2859
16.5.7.752 QUEUE_31_STATUS_A Register (offset = 31F0h) [reset = 0h]
2860
16.5.7.753 QUEUE_31_STATUS_B Register (offset = 31F4h) [reset = 0h]
2861
16.5.7.754 QUEUE_31_STATUS_C Register (offset = 31F8h) [reset = 0h]
2862
16.5.7.755 QUEUE_32_STATUS_A Register (offset = 3200h) [reset = 0h]
2863
16.5.7.756 QUEUE_32_STATUS_B Register (offset = 3204h) [reset = 0h]
2864
16.5.7.757 QUEUE_32_STATUS_C Register (offset = 3208h) [reset = 0h]
2865
16.5.7.758 QUEUE_33_STATUS_A Register (offset = 3210h) [reset = 0h]
2866
16.5.7.759 QUEUE_33_STATUS_B Register (offset = 3214h) [reset = 0h]
2867
16.5.7.760 QUEUE_33_STATUS_C Register (offset = 3218h) [reset = 0h]
2868
16.5.7.761 QUEUE_34_STATUS_A Register (offset = 3220h) [reset = 0h]
2869
16.5.7.762 QUEUE_34_STATUS_B Register (offset = 3224h) [reset = 0h]
2870
16.5.7.763 QUEUE_34_STATUS_C Register (offset = 3228h) [reset = 0h]
2871
16.5.7.764 QUEUE_35_STATUS_A Register (offset = 3230h) [reset = 0h]
2872
16.5.7.765 QUEUE_35_STATUS_B Register (offset = 3234h) [reset = 0h]
2873
16.5.7.766 QUEUE_35_STATUS_C Register (offset = 3238h) [reset = 0h]
2874
16.5.7.767 QUEUE_36_STATUS_A Register (offset = 3240h) [reset = 0h]
2875
16.5.7.768 QUEUE_36_STATUS_B Register (offset = 3244h) [reset = 0h]
2876
16.5.7.769 QUEUE_36_STATUS_C Register (offset = 3248h) [reset = 0h]
2877
16.5.7.770 QUEUE_37_STATUS_A Register (offset = 3250h) [reset = 0h]
2878
16.5.7.771 QUEUE_37_STATUS_B Register (offset = 3254h) [reset = 0h]
2879
16.5.7.772 QUEUE_37_STATUS_C Register (offset = 3258h) [reset = 0h]
2880
16.5.7.773 QUEUE_38_STATUS_A Register (offset = 3260h) [reset = 0h]
2881
16.5.7.774 QUEUE_38_STATUS_B Register (offset = 3264h) [reset = 0h]
2882
16.5.7.775 QUEUE_38_STATUS_C Register (offset = 3268h) [reset = 0h]
2883
16.5.7.776 QUEUE_39_STATUS_A Register (offset = 3270h) [reset = 0h]
2884
16.5.7.777 QUEUE_39_STATUS_B Register (offset = 3274h) [reset = 0h]
2885
16.5.7.778 QUEUE_39_STATUS_C Register (offset = 3278h) [reset = 0h]
2886
16.5.7.779 QUEUE_40_STATUS_A Register (offset = 3280h) [reset = 0h]
2887
16.5.7.780 QUEUE_40_STATUS_B Register (offset = 3284h) [reset = 0h]
2888
16.5.7.781 QUEUE_40_STATUS_C Register (offset = 3288h) [reset = 0h]
2889
16.5.7.782 QUEUE_41_STATUS_A Register (offset = 3290h) [reset = 0h]
2890
16.5.7.783 QUEUE_41_STATUS_B Register (offset = 3294h) [reset = 0h]
2891
16.5.7.784 QUEUE_41_STATUS_C Register (offset = 3298h) [reset = 0h]
2892
16.5.7.785 QUEUE_42_STATUS_A Register (offset = 32A0h) [reset = 0h]
2893
16.5.7.786 QUEUE_42_STATUS_B Register (offset = 32A4h) [reset = 0h]
2894
16.5.7.787 QUEUE_42_STATUS_C Register (offset = 32A8h) [reset = 0h]
2895
16.5.7.788 QUEUE_43_STATUS_A Register (offset = 32B0h) [reset = 0h]
2896
16.5.7.789 QUEUE_43_STATUS_B Register (offset = 32B4h) [reset = 0h]
2897
16.5.7.790 QUEUE_43_STATUS_C Register (offset = 32B8h) [reset = 0h]
2898
16.5.7.791 QUEUE_44_STATUS_A Register (offset = 32C0h) [reset = 0h]
2899
16.5.7.792 QUEUE_44_STATUS_B Register (offset = 32C4h) [reset = 0h]
2900
16.5.7.793 QUEUE_44_STATUS_C Register (offset = 32C8h) [reset = 0h]
2901
16.5.7.794 QUEUE_45_STATUS_A Register (offset = 32D0h) [reset = 0h]
2902
16.5.7.795 QUEUE_45_STATUS_B Register (offset = 32D4h) [reset = 0h]
2903
16.5.7.796 QUEUE_45_STATUS_C Register (offset = 32D8h) [reset = 0h]
2904
16.5.7.797 QUEUE_46_STATUS_A Register (offset = 32E0h) [reset = 0h]
2905
16.5.7.798 QUEUE_46_STATUS_B Register (offset = 32E4h) [reset = 0h]
2906
16.5.7.799 QUEUE_46_STATUS_C Register (offset = 32E8h) [reset = 0h]
2907
16.5.7.800 QUEUE_47_STATUS_A Register (offset = 32F0h) [reset = 0h]
2908
16.5.7.801 QUEUE_47_STATUS_B Register (offset = 32F4h) [reset = 0h]
2909
16.5.7.802 QUEUE_47_STATUS_C Register (offset = 32F8h) [reset = 0h]
2910
16.5.7.803 QUEUE_48_STATUS_A Register (offset = 3300h) [reset = 0h]
2911
16.5.7.804 QUEUE_48_STATUS_B Register (offset = 3304h) [reset = 0h]
2912
16.5.7.805 QUEUE_48_STATUS_C Register (offset = 3308h) [reset = 0h]
2913
16.5.7.806 QUEUE_49_STATUS_A Register (offset = 3310h) [reset = 0h]
2914
16.5.7.807 QUEUE_49_STATUS_B Register (offset = 3314h) [reset = 0h]
2915
16.5.7.808 QUEUE_49_STATUS_C Register (offset = 3318h) [reset = 0h]
2916
16.5.7.809 QUEUE_50_STATUS_A Register (offset = 3320h) [reset = 0h]
2917
16.5.7.810 QUEUE_50_STATUS_B Register (offset = 3324h) [reset = 0h]
2918
16.5.7.811 QUEUE_50_STATUS_C Register (offset = 3328h) [reset = 0h]
2919
16.5.7.812 QUEUE_51_STATUS_A Register (offset = 3330h) [reset = 0h]
2920
16.5.7.813 QUEUE_51_STATUS_B Register (offset = 3334h) [reset = 0h]
2921
16.5.7.814 QUEUE_51_STATUS_C Register (offset = 3338h) [reset = 0h]
2922
16.5.7.815 QUEUE_52_STATUS_A Register (offset = 3340h) [reset = 0h]
2923
16.5.7.816 QUEUE_52_STATUS_B Register (offset = 3344h) [reset = 0h]
2924
16.5.7.817 QUEUE_52_STATUS_C Register (offset = 3348h) [reset = 0h]
2925
16.5.7.818 QUEUE_53_STATUS_A Register (offset = 3350h) [reset = 0h]
2926
16.5.7.819 QUEUE_53_STATUS_B Register (offset = 3354h) [reset = 0h]
2927
16.5.7.820 QUEUE_53_STATUS_C Register (offset = 3358h) [reset = 0h]
2928
16.5.7.821 QUEUE_54_STATUS_A Register (offset = 3360h) [reset = 0h]
2929
16.5.7.822 QUEUE_54_STATUS_B Register (offset = 3364h) [reset = 0h]
2930
16.5.7.823 QUEUE_54_STATUS_C Register (offset = 3368h) [reset = 0h]
2931
16.5.7.824 QUEUE_55_STATUS_A Register (offset = 3370h) [reset = 0h]
2932
16.5.7.825 QUEUE_55_STATUS_B Register (offset = 3374h) [reset = 0h]
2933
16.5.7.826 QUEUE_55_STATUS_C Register (offset = 3378h) [reset = 0h]
2934
16.5.7.827 QUEUE_56_STATUS_A Register (offset = 3380h) [reset = 0h]
2935
16.5.7.828 QUEUE_56_STATUS_B Register (offset = 3384h) [reset = 0h]
2936
16.5.7.829 QUEUE_56_STATUS_C Register (offset = 3388h) [reset = 0h]
2937
16.5.7.830 QUEUE_57_STATUS_A Register (offset = 3390h) [reset = 0h]
2938
16.5.7.831 QUEUE_57_STATUS_B Register (offset = 3394h) [reset = 0h]
2939
16.5.7.832 QUEUE_57_STATUS_C Register (offset = 3398h) [reset = 0h]
2940
16.5.7.833 QUEUE_58_STATUS_A Register (offset = 33A0h) [reset = 0h]
2941
16.5.7.834 QUEUE_58_STATUS_B Register (offset = 33A4h) [reset = 0h]
2942
16.5.7.835 QUEUE_58_STATUS_C Register (offset = 33A8h) [reset = 0h]
2943
16.5.7.836 QUEUE_59_STATUS_A Register (offset = 33B0h) [reset = 0h]
2944
16.5.7.837 QUEUE_59_STATUS_B Register (offset = 33B4h) [reset = 0h]
2945
16.5.7.838 QUEUE_59_STATUS_C Register (offset = 33B8h) [reset = 0h]
2946
16.5.7.839 QUEUE_60_STATUS_A Register (offset = 33C0h) [reset = 0h]
2947
16.5.7.840 QUEUE_60_STATUS_B Register (offset = 33C4h) [reset = 0h]
2948
16.5.7.841 QUEUE_60_STATUS_C Register (offset = 33C8h) [reset = 0h]
2949
16.5.7.842 QUEUE_61_STATUS_A Register (offset = 33D0h) [reset = 0h]
2950
16.5.7.843 QUEUE_61_STATUS_B Register (offset = 33D4h) [reset = 0h]
2951
16.5.7.844 QUEUE_61_STATUS_C Register (offset = 33D8h) [reset = 0h]
2952
16.5.7.845 QUEUE_62_STATUS_A Register (offset = 33E0h) [reset = 0h]
2953
16.5.7.846 QUEUE_62_STATUS_B Register (offset = 33E4h) [reset = 0h]
2954
16.5.7.847 QUEUE_62_STATUS_C Register (offset = 33E8h) [reset = 0h]
2955
16.5.7.848 QUEUE_63_STATUS_A Register (offset = 33F0h) [reset = 0h]
2956
16.5.7.849 QUEUE_63_STATUS_B Register (offset = 33F4h) [reset = 0h]
2957
16.5.7.850 QUEUE_63_STATUS_C Register (offset = 33F8h) [reset = 0h]
2958
16.5.7.851 QUEUE_64_STATUS_A Register (offset = 3400h) [reset = 0h]
2959
16.5.7.852 QUEUE_64_STATUS_B Register (offset = 3404h) [reset = 0h]
2960
16.5.7.853 QUEUE_64_STATUS_C Register (offset = 3408h) [reset = 0h]
2961
16.5.7.854 QUEUE_65_STATUS_A Register (offset = 3410h) [reset = 0h]
2962
16.5.7.855 QUEUE_65_STATUS_B Register (offset = 3414h) [reset = 0h]
2963
16.5.7.856 QUEUE_65_STATUS_C Register (offset = 3418h) [reset = 0h]
2964
16.5.7.857 QUEUE_66_STATUS_A Register (offset = 3420h) [reset = 0h]
2965
16.5.7.858 QUEUE_66_STATUS_B Register (offset = 3424h) [reset = 0h]
2966
16.5.7.859 QUEUE_66_STATUS_C Register (offset = 3428h) [reset = 0h]
2967
16.5.7.860 QUEUE_67_STATUS_A Register (offset = 3430h) [reset = 0h]
2968
16.5.7.861 QUEUE_67_STATUS_B Register (offset = 3434h) [reset = 0h]
2969
16.5.7.862 QUEUE_67_STATUS_C Register (offset = 3438h) [reset = 0h]
2970
16.5.7.863 QUEUE_68_STATUS_A Register (offset = 3440h) [reset = 0h]
2971
16.5.7.864 QUEUE_68_STATUS_B Register (offset = 3444h) [reset = 0h]
2972
16.5.7.865 QUEUE_68_STATUS_C Register (offset = 3448h) [reset = 0h]
2973
16.5.7.866 QUEUE_69_STATUS_A Register (offset = 3450h) [reset = 0h]
2974
16.5.7.867 QUEUE_69_STATUS_B Register (offset = 3454h) [reset = 0h]
2975
16.5.7.868 QUEUE_69_STATUS_C Register (offset = 3458h) [reset = 0h]
2976
16.5.7.869 QUEUE_70_STATUS_A Register (offset = 3460h) [reset = 0h]
2977
16.5.7.870 QUEUE_70_STATUS_B Register (offset = 3464h) [reset = 0h]
2978
16.5.7.871 QUEUE_70_STATUS_C Register (offset = 3468h) [reset = 0h]
2979
16.5.7.872 QUEUE_71_STATUS_A Register (offset = 3470h) [reset = 0h]
2980
16.5.7.873 QUEUE_71_STATUS_B Register (offset = 3474h) [reset = 0h]
2981
16.5.7.874 QUEUE_71_STATUS_C Register (offset = 3478h) [reset = 0h]
2982
16.5.7.875 QUEUE_72_STATUS_A Register (offset = 3480h) [reset = 0h]
2983
16.5.7.876 QUEUE_72_STATUS_B Register (offset = 3484h) [reset = 0h]
2984
16.5.7.877 QUEUE_72_STATUS_C Register (offset = 3488h) [reset = 0h]
2985
16.5.7.878 QUEUE_73_STATUS_A Register (offset = 3490h) [reset = 0h]
2986
16.5.7.879 QUEUE_73_STATUS_B Register (offset = 3494h) [reset = 0h]
2987
16.5.7.880 QUEUE_73_STATUS_C Register (offset = 3498h) [reset = 0h]
2988
16.5.7.881 QUEUE_74_STATUS_A Register (offset = 34A0h) [reset = 0h]
2989
16.5.7.882 QUEUE_74_STATUS_B Register (offset = 34A4h) [reset = 0h]
2990
16.5.7.883 QUEUE_74_STATUS_C Register (offset = 34A8h) [reset = 0h]
2991
16.5.7.884 QUEUE_75_STATUS_A Register (offset = 34B0h) [reset = 0h]
2992
16.5.7.885 QUEUE_75_STATUS_B Register (offset = 34B4h) [reset = 0h]
2993
16.5.7.886 QUEUE_75_STATUS_C Register (offset = 34B8h) [reset = 0h]
2994
16.5.7.887 QUEUE_76_STATUS_A Register (offset = 34C0h) [reset = 0h]
2995
16.5.7.888 QUEUE_76_STATUS_B Register (offset = 34C4h) [reset = 0h]
2996
16.5.7.889 QUEUE_76_STATUS_C Register (offset = 34C8h) [reset = 0h]
2997
16.5.7.890 QUEUE_77_STATUS_A Register (offset = 34D0h) [reset = 0h]
2998
16.5.7.891 QUEUE_77_STATUS_B Register (offset = 34D4h) [reset = 0h]
2999
16.5.7.892 QUEUE_77_STATUS_C Register (offset = 34D8h) [reset = 0h]
3000
16.5.7.893 QUEUE_78_STATUS_A Register (offset = 34E0h) [reset = 0h]
3001
16.5.7.894 QUEUE_78_STATUS_B Register (offset = 34E4h) [reset = 0h]
3002
16.5.7.895 QUEUE_78_STATUS_C Register (offset = 34E8h) [reset = 0h]
3003
16.5.7.896 QUEUE_79_STATUS_A Register (offset = 34F0h) [reset = 0h]
3004
16.5.7.897 QUEUE_79_STATUS_B Register (offset = 34F4h) [reset = 0h]
3005
16.5.7.898 QUEUE_79_STATUS_C Register (offset = 34F8h) [reset = 0h]
3006
16.5.7.899 QUEUE_80_STATUS_A Register (offset = 3500h) [reset = 0h]
3007
16.5.7.900 QUEUE_80_STATUS_B Register (offset = 3504h) [reset = 0h]
3008
16.5.7.901 QUEUE_80_STATUS_C Register (offset = 3508h) [reset = 0h]
3009
16.5.7.902 QUEUE_81_STATUS_A Register (offset = 3510h) [reset = 0h]
3010
16.5.7.903 QUEUE_81_STATUS_B Register (offset = 3514h) [reset = 0h]
3011
16.5.7.904 QUEUE_81_STATUS_C Register (offset = 3518h) [reset = 0h]
3012
16.5.7.905 QUEUE_82_STATUS_A Register (offset = 3520h) [reset = 0h]
3013
16.5.7.906 QUEUE_82_STATUS_B Register (offset = 3524h) [reset = 0h]
3014
16.5.7.907 QUEUE_82_STATUS_C Register (offset = 3528h) [reset = 0h]
3015
16.5.7.908 QUEUE_83_STATUS_A Register (offset = 3530h) [reset = 0h]
3016
16.5.7.909 QUEUE_83_STATUS_B Register (offset = 3534h) [reset = 0h]
3017
16.5.7.910 QUEUE_83_STATUS_C Register (offset = 3538h) [reset = 0h]
3018
16.5.7.911 QUEUE_84_STATUS_A Register (offset = 3540h) [reset = 0h]
3019
16.5.7.912 QUEUE_84_STATUS_B Register (offset = 3544h) [reset = 0h]
3020
16.5.7.913 QUEUE_84_STATUS_C Register (offset = 3548h) [reset = 0h]
3021
16.5.7.914 QUEUE_85_STATUS_A Register (offset = 3550h) [reset = 0h]
3022
16.5.7.915 QUEUE_85_STATUS_B Register (offset = 3554h) [reset = 0h]
3023
16.5.7.916 QUEUE_85_STATUS_C Register (offset = 3558h) [reset = 0h]
3024
16.5.7.917 QUEUE_86_STATUS_A Register (offset = 3560h) [reset = 0h]
3025
16.5.7.918 QUEUE_86_STATUS_B Register (offset = 3564h) [reset = 0h]
3026
16.5.7.919 QUEUE_86_STATUS_C Register (offset = 3568h) [reset = 0h]
3027
16.5.7.920 QUEUE_87_STATUS_A Register (offset = 3570h) [reset = 0h]
3028
16.5.7.921 QUEUE_87_STATUS_B Register (offset = 3574h) [reset = 0h]
3029
16.5.7.922 QUEUE_87_STATUS_C Register (offset = 3578h) [reset = 0h]
3030
16.5.7.923 QUEUE_88_STATUS_A Register (offset = 3580h) [reset = 0h]
3031
16.5.7.924 QUEUE_88_STATUS_B Register (offset = 3584h) [reset = 0h]
3032
16.5.7.925 QUEUE_88_STATUS_C Register (offset = 3588h) [reset = 0h]
3033
16.5.7.926 QUEUE_89_STATUS_A Register (offset = 3590h) [reset = 0h]
3034
16.5.7.927 QUEUE_89_STATUS_B Register (offset = 3594h) [reset = 0h]
3035
16.5.7.928 QUEUE_89_STATUS_C Register (offset = 3598h) [reset = 0h]
3036
16.5.7.929 QUEUE_90_STATUS_A Register (offset = 35A0h) [reset = 0h]
3037
16.5.7.930 QUEUE_90_STATUS_B Register (offset = 35A4h) [reset = 0h]
3038
16.5.7.931 QUEUE_90_STATUS_C Register (offset = 35A8h) [reset = 0h]
3039
16.5.7.932 QUEUE_91_STATUS_A Register (offset = 35B0h) [reset = 0h]
3040
16.5.7.933 QUEUE_91_STATUS_B Register (offset = 35B4h) [reset = 0h]
3041
16.5.7.934 QUEUE_91_STATUS_C Register (offset = 35B8h) [reset = 0h]
3042
16.5.7.935 QUEUE_92_STATUS_A Register (offset = 35C0h) [reset = 0h]
3043
16.5.7.936 QUEUE_92_STATUS_B Register (offset = 35C4h) [reset = 0h]
3044
16.5.7.937 QUEUE_92_STATUS_C Register (offset = 35C8h) [reset = 0h]
3045
16.5.7.938 QUEUE_93_STATUS_A Register (offset = 35D0h) [reset = 0h]
3046
16.5.7.939 QUEUE_93_STATUS_B Register (offset = 35D4h) [reset = 0h]
3047
16.5.7.940 QUEUE_93_STATUS_C Register (offset = 35D8h) [reset = 0h]
3048
16.5.7.941 QUEUE_94_STATUS_A Register (offset = 35E0h) [reset = 0h]
3049
16.5.7.942 QUEUE_94_STATUS_B Register (offset = 35E4h) [reset = 0h]
3050
16.5.7.943 QUEUE_94_STATUS_C Register (offset = 35E8h) [reset = 0h]
3051
16.5.7.944 QUEUE_95_STATUS_A Register (offset = 35F0h) [reset = 0h]
3052
16.5.7.945 QUEUE_95_STATUS_B Register (offset = 35F4h) [reset = 0h]
3053
16.5.7.946 QUEUE_95_STATUS_C Register (offset = 35F8h) [reset = 0h]
3054
16.5.7.947 QUEUE_96_STATUS_A Register (offset = 3600h) [reset = 0h]
3055
16.5.7.948 QUEUE_96_STATUS_B Register (offset = 3604h) [reset = 0h]
3056
16.5.7.949 QUEUE_96_STATUS_C Register (offset = 3608h) [reset = 0h]
3057
16.5.7.950 QUEUE_97_STATUS_A Register (offset = 3610h) [reset = 0h]
3058
16.5.7.951 QUEUE_97_STATUS_B Register (offset = 3614h) [reset = 0h]
3059
16.5.7.952 QUEUE_97_STATUS_C Register (offset = 3618h) [reset = 0h]
3060
16.5.7.953 QUEUE_98_STATUS_A Register (offset = 3620h) [reset = 0h]
3061
16.5.7.954 QUEUE_98_STATUS_B Register (offset = 3624h) [reset = 0h]
3062
16.5.7.955 QUEUE_98_STATUS_C Register (offset = 3628h) [reset = 0h]
3063
16.5.7.956 QUEUE_99_STATUS_A Register (offset = 3630h) [reset = 0h]
3064
16.5.7.957 QUEUE_99_STATUS_B Register (offset = 3634h) [reset = 0h]
3065
16.5.7.958 QUEUE_99_STATUS_C Register (offset = 3638h) [reset = 0h]
3066
16.5.7.959 QUEUE_100_STATUS_A Register (offset = 3640h) [reset = 0h]
3067
16.5.7.960 QUEUE_100_STATUS_B Register (offset = 3644h) [reset = 0h]
3068
16.5.7.961 QUEUE_100_STATUS_C Register (offset = 3648h) [reset = 0h]
3069
16.5.7.962 QUEUE_101_STATUS_A Register (offset = 3650h) [reset = 0h]
3070
16.5.7.963 QUEUE_101_STATUS_B Register (offset = 3654h) [reset = 0h]
3071
16.5.7.964 QUEUE_101_STATUS_C Register (offset = 3658h) [reset = 0h]
3072
16.5.7.965 QUEUE_102_STATUS_A Register (offset = 3660h) [reset = 0h]
3073
16.5.7.966 QUEUE_102_STATUS_B Register (offset = 3664h) [reset = 0h]
3074
16.5.7.967 QUEUE_102_STATUS_C Register (offset = 3668h) [reset = 0h]
3075
16.5.7.968 QUEUE_103_STATUS_A Register (offset = 3670h) [reset = 0h]
3076
16.5.7.969 QUEUE_103_STATUS_B Register (offset = 3674h) [reset = 0h]
3077
16.5.7.970 QUEUE_103_STATUS_C Register (offset = 3678h) [reset = 0h]
3078
16.5.7.971 QUEUE_104_STATUS_A Register (offset = 3680h) [reset = 0h]
3079
16.5.7.972 QUEUE_104_STATUS_B Register (offset = 3684h) [reset = 0h]
3080
16.5.7.973 QUEUE_104_STATUS_C Register (offset = 3688h) [reset = 0h]
3081
16.5.7.974 QUEUE_105_STATUS_A Register (offset = 3690h) [reset = 0h]
3082
16.5.7.975 QUEUE_105_STATUS_B Register (offset = 3694h) [reset = 0h]
3083
16.5.7.976 QUEUE_105_STATUS_C Register (offset = 3698h) [reset = 0h]
3084
16.5.7.977 QUEUE_106_STATUS_A Register (offset = 36A0h) [reset = 0h]
3085
16.5.7.978 QUEUE_106_STATUS_B Register (offset = 36A4h) [reset = 0h]
3086
16.5.7.979 QUEUE_106_STATUS_C Register (offset = 36A8h) [reset = 0h]
3087
16.5.7.980 QUEUE_107_STATUS_A Register (offset = 36B0h) [reset = 0h]
3088
16.5.7.981 QUEUE_107_STATUS_B Register (offset = 36B4h) [reset = 0h]
3089
16.5.7.982 QUEUE_107_STATUS_C Register (offset = 36B8h) [reset = 0h]
3090
16.5.7.983 QUEUE_108_STATUS_A Register (offset = 36C0h) [reset = 0h]
3091
16.5.7.984 QUEUE_108_STATUS_B Register (offset = 36C4h) [reset = 0h]
3092
16.5.7.985 QUEUE_108_STATUS_C Register (offset = 36C8h) [reset = 0h]
3093
16.5.7.986 QUEUE_109_STATUS_A Register (offset = 36D0h) [reset = 0h]
3094
16.5.7.987 QUEUE_109_STATUS_B Register (offset = 36D4h) [reset = 0h]
3095
16.5.7.988 QUEUE_109_STATUS_C Register (offset = 36D8h) [reset = 0h]
3096
16.5.7.989 QUEUE_110_STATUS_A Register (offset = 36E0h) [reset = 0h]
3097
16.5.7.990 QUEUE_110_STATUS_B Register (offset = 36E4h) [reset = 0h]
3098
16.5.7.991 QUEUE_110_STATUS_C Register (offset = 36E8h) [reset = 0h]
3099
16.5.7.992 QUEUE_111_STATUS_A Register (offset = 36F0h) [reset = 0h]
3100
16.5.7.993 QUEUE_111_STATUS_B Register (offset = 36F4h) [reset = 0h]
3101
16.5.7.994 QUEUE_111_STATUS_C Register (offset = 36F8h) [reset = 0h]
3102
16.5.7.995 QUEUE_112_STATUS_A Register (offset = 3700h) [reset = 0h]
3103
16.5.7.996 QUEUE_112_STATUS_B Register (offset = 3704h) [reset = 0h]
3104
16.5.7.997 QUEUE_112_STATUS_C Register (offset = 3708h) [reset = 0h]
3105
16.5.7.998 QUEUE_113_STATUS_A Register (offset = 3710h) [reset = 0h]
3106
16.5.7.999 QUEUE_113_STATUS_B Register (offset = 3714h) [reset = 0h]
3107
16.5.7.1000 QUEUE_113_STATUS_C Register (offset = 3718h) [reset = 0h]
3108
16.5.7.1001 QUEUE_114_STATUS_A Register (offset = 3720h) [reset = 0h]
3109
16.5.7.1002 QUEUE_114_STATUS_B Register (offset = 3724h) [reset = 0h]
3110
16.5.7.1003 QUEUE_114_STATUS_C Register (offset = 3728h) [reset = 0h]
3111
16.5.7.1004 QUEUE_115_STATUS_A Register (offset = 3730h) [reset = 0h]
3112
16.5.7.1005 QUEUE_115_STATUS_B Register (offset = 3734h) [reset = 0h]
3113
16.5.7.1006 QUEUE_115_STATUS_C Register (offset = 3738h) [reset = 0h]
3114
16.5.7.1007 QUEUE_116_STATUS_A Register (offset = 3740h) [reset = 0h]
3115
16.5.7.1008 QUEUE_116_STATUS_B Register (offset = 3744h) [reset = 0h]
3116
16.5.7.1009 QUEUE_116_STATUS_C Register (offset = 3748h) [reset = 0h]
3117
16.5.7.1010 QUEUE_117_STATUS_A Register (offset = 3750h) [reset = 0h]
3118
16.5.7.1011 QUEUE_117_STATUS_B Register (offset = 3754h) [reset = 0h]
3119
16.5.7.1012 QUEUE_117_STATUS_C Register (offset = 3758h) [reset = 0h]
3120
16.5.7.1013 QUEUE_118_STATUS_A Register (offset = 3760h) [reset = 0h]
3121
16.5.7.1014 QUEUE_118_STATUS_B Register (offset = 3764h) [reset = 0h]
3122
16.5.7.1015 QUEUE_118_STATUS_C Register (offset = 3768h) [reset = 0h]
3123
16.5.7.1016 QUEUE_119_STATUS_A Register (offset = 3770h) [reset = 0h]
3124
16.5.7.1017 QUEUE_119_STATUS_B Register (offset = 3774h) [reset = 0h]
3125
16.5.7.1018 QUEUE_119_STATUS_C Register (offset = 3778h) [reset = 0h]
3126
16.5.7.1019 QUEUE_120_STATUS_A Register (offset = 3780h) [reset = 0h]
3127
16.5.7.1020 QUEUE_120_STATUS_B Register (offset = 3784h) [reset = 0h]
3128
16.5.7.1021 QUEUE_120_STATUS_C Register (offset = 3788h) [reset = 0h]
3129
16.5.7.1022 QUEUE_121_STATUS_A Register (offset = 3790h) [reset = 0h]
3130
16.5.7.1023 QUEUE_121_STATUS_B Register (offset = 3794h) [reset = 0h]
3131
16.5.7.1024 QUEUE_121_STATUS_C Register (offset = 3798h) [reset = 0h]
3132
16.5.7.1025 QUEUE_122_STATUS_A Register (offset = 37A0h) [reset = 0h]
3133
16.5.7.1026 QUEUE_122_STATUS_B Register (offset = 37A4h) [reset = 0h]
3134
16.5.7.1027 QUEUE_122_STATUS_C Register (offset = 37A8h) [reset = 0h]
3135
16.5.7.1028 QUEUE_123_STATUS_A Register (offset = 37B0h) [reset = 0h]
3136
16.5.7.1029 QUEUE_123_STATUS_B Register (offset = 37B4h) [reset = 0h]
3137
16.5.7.1030 QUEUE_123_STATUS_C Register (offset = 37B8h) [reset = 0h]
3138
16.5.7.1031 QUEUE_124_STATUS_A Register (offset = 37C0h) [reset = 0h]
3139
16.5.7.1032 QUEUE_124_STATUS_B Register (offset = 37C4h) [reset = 0h]
3140
16.5.7.1033 QUEUE_124_STATUS_C Register (offset = 37C8h) [reset = 0h]
3141
16.5.7.1034 QUEUE_125_STATUS_A Register (offset = 37D0h) [reset = 0h]
3142
16.5.7.1035 QUEUE_125_STATUS_B Register (offset = 37D4h) [reset = 0h]
3143
16.5.7.1036 QUEUE_125_STATUS_C Register (offset = 37D8h) [reset = 0h]
3144
16.5.7.1037 QUEUE_126_STATUS_A Register (offset = 37E0h) [reset = 0h]
3145
16.5.7.1038 QUEUE_126_STATUS_B Register (offset = 37E4h) [reset = 0h]
3146
16.5.7.1039 QUEUE_126_STATUS_C Register (offset = 37E8h) [reset = 0h]
3147
16.5.7.1040 QUEUE_127_STATUS_A Register (offset = 37F0h) [reset = 0h]
3148
16.5.7.1041 QUEUE_127_STATUS_B Register (offset = 37F4h) [reset = 0h]
3149
16.5.7.1042 QUEUE_127_STATUS_C Register (offset = 37F8h) [reset = 0h]
3150
16.5.7.1043 QUEUE_128_STATUS_A Register (offset = 3800h) [reset = 0h]
3151
16.5.7.1044 QUEUE_128_STATUS_B Register (offset = 3804h) [reset = 0h]
3152
16.5.7.1045 QUEUE_128_STATUS_C Register (offset = 3808h) [reset = 0h]
3153
16.5.7.1046 QUEUE_129_STATUS_A Register (offset = 3810h) [reset = 0h]
3154
16.5.7.1047 QUEUE_129_STATUS_B Register (offset = 3814h) [reset = 0h]
3155
16.5.7.1048 QUEUE_129_STATUS_C Register (offset = 3818h) [reset = 0h]
3156
16.5.7.1049 QUEUE_130_STATUS_A Register (offset = 3820h) [reset = 0h]
3157
16.5.7.1050 QUEUE_130_STATUS_B Register (offset = 3824h) [reset = 0h]
3158
16.5.7.1051 QUEUE_130_STATUS_C Register (offset = 3828h) [reset = 0h]
3159
16.5.7.1052 QUEUE_131_STATUS_A Register (offset = 3830h) [reset = 0h]
3160
16.5.7.1053 QUEUE_131_STATUS_B Register (offset = 3834h) [reset = 0h]
3161
16.5.7.1054 QUEUE_131_STATUS_C Register (offset = 3838h) [reset = 0h]
3162
16.5.7.1055 QUEUE_132_STATUS_A Register (offset = 3840h) [reset = 0h]
3163
16.5.7.1056 QUEUE_132_STATUS_B Register (offset = 3844h) [reset = 0h]
3164
16.5.7.1057 QUEUE_132_STATUS_C Register (offset = 3848h) [reset = 0h]
3165
16.5.7.1058 QUEUE_133_STATUS_A Register (offset = 3850h) [reset = 0h]
3166
16.5.7.1059 QUEUE_133_STATUS_B Register (offset = 3854h) [reset = 0h]
3167
16.5.7.1060 QUEUE_133_STATUS_C Register (offset = 3858h) [reset = 0h]
3168
16.5.7.1061 QUEUE_134_STATUS_A Register (offset = 3860h) [reset = 0h]
3169
16.5.7.1062 QUEUE_134_STATUS_B Register (offset = 3864h) [reset = 0h]
3170
16.5.7.1063 QUEUE_134_STATUS_C Register (offset = 3868h) [reset = 0h]
3171
16.5.7.1064 QUEUE_135_STATUS_A Register (offset = 3870h) [reset = 0h]
3172
16.5.7.1065 QUEUE_135_STATUS_B Register (offset = 3874h) [reset = 0h]
3173
16.5.7.1066 QUEUE_135_STATUS_C Register (offset = 3878h) [reset = 0h]
3174
16.5.7.1067 QUEUE_136_STATUS_A Register (offset = 3880h) [reset = 0h]
3175
16.5.7.1068 QUEUE_136_STATUS_B Register (offset = 3884h) [reset = 0h]
3176
16.5.7.1069 QUEUE_136_STATUS_C Register (offset = 3888h) [reset = 0h]
3177
16.5.7.1070 QUEUE_137_STATUS_A Register (offset = 3890h) [reset = 0h]
3178
16.5.7.1071 QUEUE_137_STATUS_B Register (offset = 3894h) [reset = 0h]
3179
16.5.7.1072 QUEUE_137_STATUS_C Register (offset = 3898h) [reset = 0h]
3180
16.5.7.1073 QUEUE_138_STATUS_A Register (offset = 38A0h) [reset = 0h]
3181
16.5.7.1074 QUEUE_138_STATUS_B Register (offset = 38A4h) [reset = 0h]
3182
16.5.7.1075 QUEUE_138_STATUS_C Register (offset = 38A8h) [reset = 0h]
3183
16.5.7.1076 QUEUE_139_STATUS_A Register (offset = 38B0h) [reset = 0h]
3184
16.5.7.1077 QUEUE_139_STATUS_B Register (offset = 38B4h) [reset = 0h]
3185
16.5.7.1078 QUEUE_139_STATUS_C Register (offset = 38B8h) [reset = 0h]
3186
16.5.7.1079 QUEUE_140_STATUS_A Register (offset = 38C0h) [reset = 0h]
3187
16.5.7.1080 QUEUE_140_STATUS_B Register (offset = 38C4h) [reset = 0h]
3188
16.5.7.1081 QUEUE_140_STATUS_C Register (offset = 38C8h) [reset = 0h]
3189
16.5.7.1082 QUEUE_141_STATUS_A Register (offset = 38D0h) [reset = 0h]
3190
16.5.7.1083 QUEUE_141_STATUS_B Register (offset = 38D4h) [reset = 0h]
3191
16.5.7.1084 QUEUE_141_STATUS_C Register (offset = 38D8h) [reset = 0h]
3192
16.5.7.1085 QUEUE_142_STATUS_A Register (offset = 38E0h) [reset = 0h]
3193
16.5.7.1086 QUEUE_142_STATUS_B Register (offset = 38E4h) [reset = 0h]
3194
16.5.7.1087 QUEUE_142_STATUS_C Register (offset = 38E8h) [reset = 0h]
3195
16.5.7.1088 QUEUE_143_STATUS_A Register (offset = 38F0h) [reset = 0h]
3196
16.5.7.1089 QUEUE_143_STATUS_B Register (offset = 38F4h) [reset = 0h]
3197
16.5.7.1090 QUEUE_143_STATUS_C Register (offset = 38F8h) [reset = 0h]
3198
16.5.7.1091 QUEUE_144_STATUS_A Register (offset = 3900h) [reset = 0h]
3199
16.5.7.1092 QUEUE_144_STATUS_B Register (offset = 3904h) [reset = 0h]
3200
16.5.7.1093 QUEUE_144_STATUS_C Register (offset = 3908h) [reset = 0h]
3201
16.5.7.1094 QUEUE_145_STATUS_A Register (offset = 3910h) [reset = 0h]
3202
16.5.7.1095 QUEUE_145_STATUS_B Register (offset = 3914h) [reset = 0h]
3203
16.5.7.1096 QUEUE_145_STATUS_C Register (offset = 3918h) [reset = 0h]
3204
16.5.7.1097 QUEUE_146_STATUS_A Register (offset = 3920h) [reset = 0h]
3205
16.5.7.1098 QUEUE_146_STATUS_B Register (offset = 3924h) [reset = 0h]
3206
16.5.7.1099 QUEUE_146_STATUS_C Register (offset = 3928h) [reset = 0h]
3207
16.5.7.1100 QUEUE_147_STATUS_A Register (offset = 3930h) [reset = 0h]
3208
16.5.7.1101 QUEUE_147_STATUS_B Register (offset = 3934h) [reset = 0h]
3209
16.5.7.1102 QUEUE_147_STATUS_C Register (offset = 3938h) [reset = 0h]
3210
16.5.7.1103 QUEUE_148_STATUS_A Register (offset = 3940h) [reset = 0h]
3211
16.5.7.1104 QUEUE_148_STATUS_B Register (offset = 3944h) [reset = 0h]
3212
16.5.7.1105 QUEUE_148_STATUS_C Register (offset = 3948h) [reset = 0h]
3213
16.5.7.1106 QUEUE_149_STATUS_A Register (offset = 3950h) [reset = 0h]
3214
16.5.7.1107 QUEUE_149_STATUS_B Register (offset = 3954h) [reset = 0h]
3215
16.5.7.1108 QUEUE_149_STATUS_C Register (offset = 3958h) [reset = 0h]
3216
16.5.7.1109 QUEUE_150_STATUS_A Register (offset = 3960h) [reset = 0h]
3217
16.5.7.1110 QUEUE_150_STATUS_B Register (offset = 3964h) [reset = 0h]
3218
16.5.7.1111 QUEUE_150_STATUS_C Register (offset = 3968h) [reset = 0h]
3219
16.5.7.1112 QUEUE_151_STATUS_A Register (offset = 3970h) [reset = 0h]
3220
16.5.7.1113 QUEUE_151_STATUS_B Register (offset = 3974h) [reset = 0h]
3221
16.5.7.1114 QUEUE_151_STATUS_C Register (offset = 3978h) [reset = 0h]
3222
16.5.7.1115 QUEUE_152_STATUS_A Register (offset = 3980h) [reset = 0h]
3223
16.5.7.1116 QUEUE_152_STATUS_B Register (offset = 3984h) [reset = 0h]
3224
16.5.7.1117 QUEUE_152_STATUS_C Register (offset = 3988h) [reset = 0h]
3225
16.5.7.1118 QUEUE_153_STATUS_A Register (offset = 3990h) [reset = 0h]
3226
16.5.7.1119 QUEUE_153_STATUS_B Register (offset = 3994h) [reset = 0h]
3227
16.5.7.1120 QUEUE_153_STATUS_C Register (offset = 3998h) [reset = 0h]
3228
16.5.7.1121 QUEUE_154_STATUS_A Register (offset = 39A0h) [reset = 0h]
3229
16.5.7.1122 QUEUE_154_STATUS_B Register (offset = 39A4h) [reset = 0h]
3230
16.5.7.1123 QUEUE_154_STATUS_C Register (offset = 39A8h) [reset = 0h]
3231
16.5.7.1124 QUEUE_155_STATUS_A Register (offset = 39B0h) [reset = 0h]
3232
16.5.7.1125 QUEUE_155_STATUS_B Register (offset = 39B4h) [reset = 0h]
3233
16.5.7.1126 QUEUE_155_STATUS_C Register (offset = 39B8h) [reset = 0h]
3234
17 Interprocessor Communication
3235
17.1 Mailbox
3236
17.1.1 Introduction
3236
17.1.1.1 Features
3236
17.1.1.2 Unsupported Features
3236
17.1.2 Integration
3237
17.1.2.1 Mailbox Connectivity Attributes
3237
17.1.2.2 Mailbox Clock and Reset Management
3237
17.1.2.3 Mailbox Pin List
3238
17.1.3 Functional Description
3238
17.1.3.1 Mailbox Block Diagram
3238
17.1.3.2 Software Reset
3239
17.1.3.3 Power Management
3239
17.1.3.4 Interrupt Requests
3240
17.1.3.5 Assignment
3241
17.1.3.5.1 Description
3241
17.1.3.6 Sending and Receiving Messages
3241
17.1.3.6.1 Description
3241
17.1.3.7 16-Bit Register Access
3242
17.1.3.7.1 Description
3242
17.1.4 Programming Guide
3242
17.1.4.1 Low-level Programming Models
3242
17.1.4.1.1 Global Initialization
3242
17.1.4.1.2 Operational Modes Configuration
3243
17.1.4.1.3 Events Servicing
3244
17.1.5 MAILBOX Registers
3245
17.1.5.1 REVISION Register (offset = 0h) [reset = 400h]
3248
17.1.5.2 SYSCONFIG Register (offset = 10h) [reset = 8h]
3249
17.1.5.3 MESSAGE_0 Register (offset = 40h) [reset = 0h]
3250
17.1.5.4 MESSAGE_1 Register (offset = 44h) [reset = 0h]
3251
17.1.5.5 MESSAGE_2 Register (offset = 48h) [reset = 0h]
3252
17.1.5.6 MESSAGE_3 Register (offset = 4Ch) [reset = 0h]
3253
17.1.5.7 MESSAGE_4 Register (offset = 50h) [reset = 0h]
3254
17.1.5.8 MESSAGE_5 Register (offset = 54h) [reset = 0h]
3255
17.1.5.9 MESSAGE_6 Register (offset = 58h) [reset = 0h]
3256
17.1.5.10 MESSAGE_7 Register (offset = 5Ch) [reset = 0h]
3257
17.1.5.11 FIFOSTATUS_0 Register (offset = 80h) [reset = 0h]
3258
17.1.5.12 FIFOSTATUS_1 Register (offset = 84h) [reset = 0h]
3259
17.1.5.13 FIFOSTATUS_2 Register (offset = 88h) [reset = 0h]
3260
17.1.5.14 FIFOSTATUS_3 Register (offset = 8Ch) [reset = 0h]
3261
17.1.5.15 FIFOSTATUS_4 Register (offset = 90h) [reset = 0h]
3262
17.1.5.16 FIFOSTATUS_5 Register (offset = 94h) [reset = 0h]
3263
17.1.5.17 FIFOSTATUS_6 Register (offset = 98h) [reset = 0h]
3264
17.1.5.18 FIFOSTATUS_7 Register (offset = 9Ch) [reset = 0h]
3265
17.1.5.19 MSGSTATUS_0 Register (offset = C0h) [reset = 0h]
3266
17.1.5.20 MSGSTATUS_1 Register (offset = C4h) [reset = 0h]
3267
17.1.5.21 MSGSTATUS_2 Register (offset = C8h) [reset = 0h]
3268
17.1.5.22 MSGSTATUS_3 Register (offset = CCh) [reset = 0h]
3269
17.1.5.23 MSGSTATUS_4 Register (offset = D0h) [reset = 0h]
3270
17.1.5.24 MSGSTATUS_5 Register (offset = D4h) [reset = 0h]
3271
17.1.5.25 MSGSTATUS_6 Register (offset = D8h) [reset = 0h]
3272
17.1.5.26 MSGSTATUS_7 Register (offset = DCh) [reset = 0h]
3273
17.1.5.27 IRQSTATUS_RAW_0 Register (offset = 100h) [reset = 0h]
3274
17.1.5.28 IRQSTATUS_CLR_0 Register (offset = 104h) [reset = 0h]
3276
17.1.5.29 IRQENABLE_SET_0 Register (offset = 108h) [reset = 0h]
3278
17.1.5.30 IRQENABLE_CLR_0 Register (offset = 10Ch) [reset = 0h]
3280
17.1.5.31 IRQSTATUS_RAW_1 Register (offset = 110h) [reset = 0h]
3282
17.1.5.32 IRQSTATUS_CLR_1 Register (offset = 114h) [reset = 0h]
3284
17.1.5.33 IRQENABLE_SET_1 Register (offset = 118h) [reset = 0h]
3286
17.1.5.34 IRQENABLE_CLR_1 Register (offset = 11Ch) [reset = 0h]
3288
17.1.5.35 IRQSTATUS_RAW_2 Register (offset = 120h) [reset = 0h]
3290
17.1.5.36 IRQSTATUS_CLR_2 Register (offset = 124h) [reset = 0h]
3292
17.1.5.37 IRQENABLE_SET_2 Register (offset = 128h) [reset = 0h]
3294
17.1.5.38 IRQENABLE_CLR_2 Register (offset = 12Ch) [reset = 0h]
3296
17.1.5.39 IRQSTATUS_RAW_3 Register (offset = 130h) [reset = 0h]
3298
17.1.5.40 IRQSTATUS_CLR_3 Register (offset = 134h) [reset = 0h]
3300
17.1.5.41 IRQENABLE_SET_3 Register (offset = 138h) [reset = 0h]
3302
17.1.5.42 IRQENABLE_CLR_3 Register (offset = 13Ch) [reset = 0h]
3304
17.2 Spinlock
3306
17.2.1 SPINLOCK Registers
3306
17.2.1.1 REV Register (offset = 0h) [reset = 50020000h]
3309
17.2.1.2 SYSCONFIG Register (offset = 10h) [reset = 11h]
3310
17.2.1.3 SYSTATUS Register (offset = 14h) [reset = 1000001h]
3311
17.2.1.4 LOCK_REG_0 Register (offset = 800h) [reset = 0h]
3312
17.2.1.5 LOCK_REG_1 Register (offset = 804h) [reset = 0h]
3313
17.2.1.6 LOCK_REG_2 Register (offset = 808h) [reset = 0h]
3314
17.2.1.7 LOCK_REG_3 Register (offset = 80Ch) [reset = 0h]
3315
17.2.1.8 LOCK_REG_4 Register (offset = 810h) [reset = 0h]
3316
17.2.1.9 LOCK_REG_5 Register (offset = 814h) [reset = 0h]
3317
17.2.1.10 LOCK_REG_6 Register (offset = 818h) [reset = 0h]
3318
17.2.1.11 LOCK_REG_7 Register (offset = 81Ch) [reset = 0h]
3319
17.2.1.12 LOCK_REG_8 Register (offset = 820h) [reset = 0h]
3320
17.2.1.13 LOCK_REG_9 Register (offset = 824h) [reset = 0h]
3321
17.2.1.14 LOCK_REG_10 Register (offset = 828h) [reset = 0h]
3322
17.2.1.15 LOCK_REG_11 Register (offset = 82Ch) [reset = 0h]
3323
17.2.1.16 LOCK_REG_12 Register (offset = 830h) [reset = 0h]
3324
17.2.1.17 LOCK_REG_13 Register (offset = 834h) [reset = 0h]
3325
17.2.1.18 LOCK_REG_14 Register (offset = 838h) [reset = 0h]
3326
17.2.1.19 LOCK_REG_15 Register (offset = 83Ch) [reset = 0h]
3327
17.2.1.20 LOCK_REG_16 Register (offset = 840h) [reset = 0h]
3328
17.2.1.21 LOCK_REG_17 Register (offset = 844h) [reset = 0h]
3329
17.2.1.22 LOCK_REG_18 Register (offset = 848h) [reset = 0h]
3330
17.2.1.23 LOCK_REG_19 Register (offset = 84Ch) [reset = 0h]
3331
17.2.1.24 LOCK_REG_20 Register (offset = 850h) [reset = 0h]
3332
17.2.1.25 LOCK_REG_21 Register (offset = 854h) [reset = 0h]
3333
17.2.1.26 LOCK_REG_22 Register (offset = 858h) [reset = 0h]
3334
17.2.1.27 LOCK_REG_23 Register (offset = 85Ch) [reset = 0h]
3335
17.2.1.28 LOCK_REG_24 Register (offset = 860h) [reset = 0h]
3336
17.2.1.29 LOCK_REG_25 Register (offset = 864h) [reset = 0h]
3337
17.2.1.30 LOCK_REG_26 Register (offset = 868h) [reset = 0h]
3338
17.2.1.31 LOCK_REG_27 Register (offset = 86Ch) [reset = 0h]
3339
17.2.1.32 LOCK_REG_28 Register (offset = 870h) [reset = 0h]
3340
17.2.1.33 LOCK_REG_29 Register (offset = 874h) [reset = 0h]
3341
17.2.1.34 LOCK_REG_30 Register (offset = 878h) [reset = 0h]
3342
17.2.1.35 LOCK_REG_31 Register (offset = 87Ch) [reset = 0h]
3343
18 Multimedia Card (MMC)
3344
18.1 Introduction
3345
18.1.1 MMCHS Features
3345
18.1.2 Unsupported MMCHS Features
3345
18.2 Integration
3346
18.2.1 MMCHS Connectivity Attributes
3347
18.2.2 MMCHS Clock and Reset Management
3348
18.2.3 MMCHS Pin List
3348
18.3 Functional Description
3350
18.3.1 MMC/SD/SDIO Functional Modes
3350
18.3.1.1 MMC/SD/SDIO Connected to an MMC, an SD Card, or an SDIO Card
3350
18.3.1.2 Protocol and Data Format
3351
18.3.1.2.1 Protocol
3353
18.3.1.2.2 Data Format
3355
18.3.2 Resets
3357
18.3.2.1 Hardware Reset
3357
18.3.2.2 Software Reset
3357
18.3.3 Power Management
3358
18.3.3.1 Normal Mode
3358
18.3.3.2 Idle Mode
3358
18.3.3.3 Transition from Normal Mode to Smart-Idle Mode
3359
18.3.3.4 Transition from Smart-Idle Mode to Normal Mode
3359
18.3.3.5 Force-Idle Mode
3359
18.3.3.6 Local Power Management
3360
18.3.4 Interrupt Requests
3361
18.3.4.1 Interrupt-Driven Operation
3363
18.3.4.2 Polling
3363
18.3.5 DMA Modes
3363
18.3.5.1 DMA Slave Mode Operations
3363
18.3.5.1.1 DMA Receive Mode
3364
18.3.5.1.2 DMA Transmit Mode
3365
18.3.6 Mode Selection
3366
18.3.7 Buffer Management
3366
18.3.7.1 Data Buffer
3366
18.3.7.1.1 Memory Size, Block Length, and Buffer Management Relationship
3368
18.3.7.1.2 Data Buffer Status
3369
18.3.8 Transfer Process
3369
18.3.8.1 Different Types of Commands
3369
18.3.8.2 Different Types of Responses
3369
18.3.9 Transfer or Command Status and Error Reporting
3370
18.3.9.1 Busy Timeout for R1b, R5b Response Type
3371
18.3.9.2 Busy Timeout After Write CRC Status
3371
18.3.9.3 Write CRC Status Timeout
3372
18.3.9.4 Read Data Timeout
3372
18.3.9.5 Boot Acknowledge Timeout
3373
18.3.10 Auto Command 12 Timings
3375
18.3.10.1 Auto Command 12 Timings During Write Transfer
3375
18.3.10.2 Auto Command 12 Timings During Read Transfer
3376
18.3.11 Transfer Stop
3377
18.3.12 Output Signals Generation
3378
18.3.12.1 Generation on Falling Edge of MMC Clock
3378
18.3.12.2 Generation on Rising Edge of MMC Clock
3378
18.3.13 Card Boot Mode Management
3380
18.3.13.1 Boot Mode Using CMD0
3380
18.3.13.2 Boot Mode With CMD Held Low
3381
18.3.14 CE-ATA Command Completion Disable Management
3382
18.3.15 Test Registers
3382
18.3.16 MMC/SD/SDIO Hardware Status Features
3383
18.4 Low-Level Programming Models
3384
18.4.1 Surrounding Modules Global Initialization
3384
18.4.2 MMC/SD/SDIO Controller Initialization Flow
3384
18.4.2.1 Enable OCP and CLKADPI Clocks
3384
18.4.2.2 SD Soft Reset Flow
3385
18.4.2.3 Set SD Default Capabilities
3385
18.4.2.4 Wake-Up Configuration
3385
18.4.2.5 MMC Host and Bus Configuration
3386
18.4.3 Operational Modes Configuration
3387
18.4.3.1 Basic Operations for MMC/SD/SDIO Host Controller
3387
18.4.3.2 Card Detection, Identification, and Selection
3387
18.5 Multimedia Card Registers
3389
18.5.1 MULTIMEDIA_CARD Registers
3389
18.5.1.1 SD_SYSCONFIG Register (offset = 110h) [reset = 0h]
3390
18.5.1.2 SD_SYSSTATUS Register (offset = 114h) [reset = 0h]
3392
18.5.1.3 SD_CSRE Register (offset = 124h) [reset = 0h]
3393
18.5.1.4 SD_SYSTEST Register (offset = 128h) [reset = 0h]
3394
18.5.1.5 SD_CON Register (offset = 12Ch) [reset = 0h]
3398
18.5.1.6 SD_PWCNT Register (offset = 130h) [reset = 0h]
3402
18.5.1.7 SD_SDMASA Register (offset = 200h) [reset = 0h]
3403
18.5.1.8 SD_BLK Register (offset = 204h) [reset = 0h]
3404
18.5.1.9 SD_ARG Register (offset = 208h) [reset = 0h]
3405
18.5.1.10 SD_CMD Register (offset = 20Ch) [reset = 0h]
3406
18.5.1.11 SD_RSP10 Register (offset = 210h) [reset = 0h]
3411
18.5.1.12 SD_RSP32 Register (offset = 214h) [reset = 0h]
3412
18.5.1.13 SD_RSP54 Register (offset = 218h) [reset = 0h]
3413
18.5.1.14 SD_RSP76 Register (offset = 21Ch) [reset = 0h]
3414
18.5.1.15 SD_DATA Register (offset = 220h) [reset = 0h]
3415
18.5.1.16 SD_PSTATE Register (offset = 224h) [reset = 0h]
3416
18.5.1.17 SD_HCTL Register (offset = 228h) [reset = 0h]
3419
18.5.1.18 SD_SYSCTL Register (offset = 22Ch) [reset = 0h]
3422
18.5.1.19 SD_STAT Register (offset = 230h) [reset = 0h]
3424
18.5.1.20 SD_IE Register (offset = 234h) [reset = 0h]
3429
18.5.1.21 SD_ISE Register (offset = 238h) [reset = 0h]
3432
18.5.1.22 SD_AC12 Register (offset = 23Ch) [reset = 0h]
3435
18.5.1.23 SD_CAPA Register (offset = 240h) [reset = 0h]
3437
18.5.1.24 SD_CUR_CAPA Register (offset = 248h) [reset = 0h]
3439
18.5.1.25 SD_FE Register (offset = 250h) [reset = 0h]
3440
18.5.1.26 SD_ADMAES Register (offset = 254h) [reset = 0h]
3442
18.5.1.27 SD_ADMASAL Register (offset = 258h) [reset = 0h]
3443
18.5.1.28 SD_ADMASAH Register (offset = 25Ch) [reset = 0h]
3444
18.5.1.29 SD_REV Register (offset = 2FCh) [reset = 31010000h]
3445
19 Universal Asynchronous Receiver/Transmitter (UART)
3446
19.1 Introduction
3447
19.1.1 UART Mode Features
3447
19.1.2 IrDA Mode Features
3447
19.1.3 CIR Mode Features
3447
19.1.4 Unsupported UART Features
3447
19.2 Integration
3449
19.2.1 UART Connectivity Attributes
3449
19.2.2 UART Clock and Reset Management
3450
19.2.3 UART Pin List
3452
19.3 Functional Description
3453
19.3.1 Block Diagram
3453
19.3.2 Clock Configuration
3454
19.3.3 Software Reset
3454
19.3.4 Power Management
3454
19.3.4.1 UART Mode Power Management
3454
19.3.4.1.1 Module Power Saving
3454
19.3.4.1.2 System Power Saving
3455
19.3.4.2 IrDA/CIR Mode Power Management
3455
19.3.4.2.1 Module Power Saving
3455
19.3.4.2.2 System Power Saving
3455
19.3.4.3 Local Power Management
3455
19.3.5 Interrupt Requests
3456
19.3.5.1 UART Mode Interrupt Management
3456
19.3.5.1.1 UART Interrupts
3456
19.3.5.2 Wake-Up Interrupt
3457
19.3.5.3 IrDA Mode Interrupt Management
3457
19.3.5.3.1 IrDA Interrupts
3457
19.3.5.4 CIR Mode Interrupt Management
3458
19.3.5.4.1 CIR Interrupts
3458
19.3.6 FIFO Management
3459
19.3.6.1 FIFO Trigger
3460
19.3.6.1.1 Transmit FIFO Trigger
3460
19.3.6.1.2 Receive FIFO Trigger
3460
19.3.6.2 FIFO Interrupt Mode
3461
19.3.6.3 FIFO Polled Mode Operation
3462
19.3.6.4 FIFO DMA Mode Operation
3462
19.3.6.4.1 DMA Transfers (DMA Mode 1, 2, or 3)
3463
19.3.6.4.2 DMA Transmission
3466
19.3.6.4.3 DMA Reception
3467
19.3.7 Mode Selection
3467
19.3.7.1 Register Access Modes
3467
19.3.7.1.1 Operational Mode and Configuration Modes
3467
19.3.7.1.2 Register Access Submode
3468
19.3.7.1.3 Registers Available for the Register Access Modes
3468
19.3.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
3469
19.3.7.2.1 Registers Available for the UART Function
3470
19.3.7.2.2 Registers Available for the IrDA Function
3471
19.3.7.2.3 Registers Available for the CIR Function
3472
19.3.8 Protocol Formatting
3473
19.3.8.1 UART Mode
3474
19.3.8.1.1 UART Clock Generation: Baud Rate Generation
3474
19.3.8.1.2 Choosing the Appropriate Divisor Value
3475
19.3.8.1.3 UART Data Formatting
3475
19.3.8.2 IrDA Mode
3480
19.3.8.2.1 SIR Mode
3480
19.3.8.2.2 MIR Mode
3483
19.3.8.2.3 FIR Mode
3484
19.3.8.2.4 IrDA Clock Generation: Baud Generator
3485
19.3.8.2.5 Choosing the Appropriate Divisor Value
3485
19.3.8.2.6 IrDA Data Formatting
3486
19.3.8.2.7 SIR Mode Data Formatting
3488
19.3.8.2.8 MIR and FIR Mode Data Formatting
3488
19.3.8.3 CIR Mode
3489
19.3.8.3.1 Consumer IR Encoding
3489
19.3.8.3.2 CIR Mode Operation
3491
19.3.8.3.3 Carrier Modulation
3492
19.3.8.3.4 Frequency Divider Values
3495
19.4 UART/IrDA/CIR Basic Programming Model
3496
19.4.1 UART Programming Model
3496
19.4.1.1 Quick Start
3496
19.4.1.1.1 Software Reset
3496
19.4.1.1.2 FIFOs and DMA Settings
3496
19.4.1.1.3 Protocol, Baud Rate, and Interrupt Settings
3497
19.4.1.2 Hardware and Software Flow Control Configuration
3499
19.4.1.2.1 Hardware Flow Control Configuration
3499
19.4.1.2.2 Software Flow Control Configuration
3499
19.4.2 IrDA Programming Model
3502
19.4.2.1 SIR Mode
3502
19.4.2.1.1 Receive
3502
19.4.2.1.2 Transmit
3502
19.4.2.2 MIR Mode
3503
19.4.2.2.1 Receive
3503
19.4.2.2.2 Transmit
3503
19.4.2.3 FIR Mode
3504
19.4.2.3.1 Receive
3504
19.4.2.3.2 Transmit
3504
19.5 UART Registers
3505
19.5.1 UART Registers
3505
19.5.1.1 Receiver Holding Register (RHR)
3507
19.5.1.2 Transmit Holding Register (THR)
3507
19.5.1.3 Interrupt Enable Register (IER) - UART Mode
3508
19.5.1.4 Interrupt Enable Register (IER) - IrDA Mode
3509
19.5.1.5 Interrupt Enable Register (IER) - CIR Mode
3510
19.5.1.6 Interrupt Identification Register (IIR) - UART Mode
3511
19.5.1.7 Interrupt Identification Register (IIR) - IrDA Mode
3512
19.5.1.8 Interrupt Identification Register (IIR) - CIR Mode
3513
19.5.1.9 FIFO Control Register (FCR)
3514
19.5.1.10 Line Control Register (LCR)
3515
19.5.1.11 Modem Control Register (MCR)
3516
19.5.1.12 Line Status Register (LSR) - UART Mode
3517
19.5.1.13 Line Status Register (LSR) - IrDA Mode
3518
19.5.1.14 Line Status Register (LSR) - CIR Mode
3519
19.5.1.15 Modem Status Register (MSR)
3520
19.5.1.16 Transmission Control Register (TCR)
3521
19.5.1.17 Scratchpad Register (SPR)
3521
19.5.1.18 Trigger Level Register (TLR)
3522
19.5.1.19 Mode Definition Register 1 (MDR1)
3523
19.5.1.20 Mode Definition Register 2 (MDR2)
3524
19.5.1.21 Status FIFO Line Status Register (SFLSR)
3525
19.5.1.22 RESUME Register
3525
19.5.1.23 Status FIFO Register Low (SFREGL)
3526
19.5.1.24 Status FIFO Register High (SFREGH)
3526
19.5.1.25 BOF Control Register (BLR)
3527
19.5.1.26 Auxiliary Control Register (ACREG)
3528
19.5.1.27 Supplementary Control Register (SCR)
3529
19.5.1.28 Supplementary Status Register (SSR)
3530
19.5.1.29 BOF Length Register (EBLR)
3531
19.5.1.30 Module Version Register (MVR)
3532
19.5.1.31 System Configuration Register (SYSC)
3533
19.5.1.32 System Status Register (SYSS)
3533
19.5.1.33 Wake-Up Enable Register (WER)
3534
19.5.1.34 Carrier Frequency Prescaler Register (CFPS)
3535
19.5.1.35 Divisor Latches Low Register (DLL)
3536
19.5.1.36 Divisor Latches High Register (DLH)
3536
19.5.1.37 Enhanced Feature Register (EFR)
3537
19.5.1.38 XON1/ADDR1 Register
3538
19.5.1.39 XON2/ADDR2 Register
3538
19.5.1.40 XOFF1 Register
3539
19.5.1.41 XOFF2 Register
3539
19.5.1.42 Transmit Frame Length Low Register (TXFLL)
3540
19.5.1.43 Transmit Frame Length High Register (TXFLH)
3540
19.5.1.44 Received Frame Length Low Register (RXFLL)
3541
19.5.1.45 Received Frame Length High Register (RXFLH)
3541
19.5.1.46 UART Autobauding Status Register (UASR)
3542
19.5.1.47 Received FIFO Level (RXFIFO_LVL) Register
3543
19.5.1.48 Transmit FIFO Level (TXFIFO_LVL) Register
3544
19.5.1.49 IER2 Register
3545
19.5.1.50 ISR2 Register
3546
19.5.1.51 FREQ_SEL Register
3547
19.5.1.52 Mode Definition Register 3 (MDR3) Register
3548
19.5.1.53 TX_DMA_THRESHOLD Register
3549
20 Timers
3550
20.1 DMTimer
3551
20.1.1 Introduction
3551
20.1.1.1 Overview
3551
20.1.1.2 Features
3551
20.1.1.3 Functional Block Diagram
3552
20.1.2 Integration
3553
20.1.2.1 Timer Connectivity Attributes
3554
20.1.2.2 Timer Clock and Reset Management
3555
20.1.2.3 Timer Clock Signals
3555
20.1.2.4 Timer Pin List
3556
20.1.3 Functional Description
3557
20.1.3.1 Functional Description
3557
20.1.3.1.1 Timer Mode Functionality
3557
20.1.3.1.2 Capture Mode Functionality
3557
20.1.3.1.3 Compare Mode Functionality
3559
20.1.3.1.4 Prescaler Functionality
3559
20.1.3.1.5 Pulse-Width Modulation
3560
20.1.3.1.6 Timer Counting Rate
3562
20.1.3.1.7 Dual Mode Timer Under Emulation
3562
20.1.3.2 Accessing Registers
3563
20.1.3.2.1 Programming the Timer Registers
3563
20.1.3.2.2 Reading the Timer Registers
3563
20.1.3.2.3 OCP Error Generation
3563
20.1.3.3 Posted Mode Selection
3563
20.1.3.4 Write Registers Access
3564
20.1.3.4.1 Write Posted
3564
20.1.3.4.2 Write Non-Posted
3565
20.1.3.5 Read Registers Access
3565
20.1.3.5.1 Read Posted
3565
20.1.3.5.2 Read Non-Posted
3565
20.1.4 Use Cases
3566
20.1.5 TIMER Registers
3566
20.1.5.1 TIDR Register (offset = 00h) [reset = 40000100h]
3567
20.1.5.2 TIOCP_CFG Register (offset = 10h) [reset = 0h]
3568
20.1.5.3 IRQ_EOI Register (offset = 20h) [reset = 0h]
3569
20.1.5.4 IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
3570
20.1.5.5 IRQSTATUS Register (offset = 28h) [reset = 0h]
3571
20.1.5.6 IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
3572
20.1.5.7 IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
3573
20.1.5.8 IRQWAKEEN Register (offset = 34h) [reset = 0h]
3574
20.1.5.9 TCLR Register (offset = 38h) [reset = 0h]
3575
20.1.5.10 TCRR Register (offset = 3Ch) [reset = 0h]
3577
20.1.5.11 TLDR Register (offset = 40h) [reset = 0h]
3578
20.1.5.12 TTGR Register (offset = 44h) [reset = FFFFFFFFh]
3579
20.1.5.13 TWPS Register (offset = 48h) [reset = 0h]
3580
20.1.5.14 TMAR Register (offset = 4Ch) [reset = 0h]
3581
20.1.5.15 TCAR1 Register (offset = 50h) [reset = 0h]
3582
20.1.5.16 TSICR Register (offset = 54h) [reset = 0h]
3583
20.1.5.17 TCAR2 Register (offset = 58h) [reset = 0h]
3584
20.2 DMTimer 1ms
3585
20.2.1 Introduction
3585
20.2.2 Integration
3587
20.2.2.1 Timer Connectivity Attributes
3587
20.2.2.2 Timer Clock and Reset Manangement
3587
20.2.2.3 Timer Clock Signals
3588
20.2.3 Functional Description
3589
20.2.3.1 Timer Mode Functionality
3589
20.2.3.1.1 1 ms Tick Generation
3589
20.2.3.2 Capture Mode Functionality
3591
20.2.3.3 Compare Mode Functionality
3592
20.2.3.4 Prescaler Functionality
3593
20.2.3.5 Pulse-Width Modulation
3593
20.2.3.6 Timer Interrupt Control
3594
20.2.3.7 Sleep Mode Request and Acknowledge
3595
20.2.3.7.1 Wake-up Line Release
3596
20.2.3.8 Timer Counting Rate
3596
20.2.3.9 Dual Mode Timer Under Emulation
3597
20.2.4 Use Cases
3597
20.2.5 DMTIMER_1MS Registers
3597
20.2.5.1 TIDR Register (offset = 0h) [reset = 15h]
3599
20.2.5.2 TIOCP_CFG Register (offset = 10h) [reset = 0h]
3600
20.2.5.3 TISTAT Register (offset = 14h) [reset = 0h]
3601
20.2.5.4 TISR Register (offset = 18h) [reset = 0h]
3602
20.2.5.5 TIER Register (offset = 1Ch) [reset = 0h]
3603
20.2.5.6 TWER Register (offset = 20h) [reset = 0h]
3604
20.2.5.7 TCLR Register (offset = 24h) [reset = 0h]
3605
20.2.5.8 TCRR Register (offset = 28h) [reset = 0h]
3607
20.2.5.9 TLDR Register (offset = 2Ch) [reset = 0h]
3608
20.2.5.10 TTGR Register (offset = 30h) [reset = FFFFFFFFh]
3609
20.2.5.11 TWPS Register (offset = 34h) [reset = 0h]
3610
20.2.5.12 TMAR Register (offset = 38h) [reset = 0h]
3612
20.2.5.13 TCAR1 Register (offset = 3Ch) [reset = 0h]
3613
20.2.5.14 TSICR Register (offset = 40h) [reset = 0h]
3614
20.2.5.15 TCAR2 Register (offset = 44h) [reset = 0h]
3615
20.2.5.16 TPIR Register (offset = 48h) [reset = 0h]
3616
20.2.5.17 TNIR Register (offset = 4Ch) [reset = 0h]
3617
20.2.5.18 TCVR Register (offset = 50h) [reset = 0h]
3618
20.2.5.19 TOCR Register (offset = 54h) [reset = 0h]
3619
20.2.5.20 TOWR Register (offset = 58h) [reset = 0h]
3620
20.3 RTC_SS
3621
20.3.1 Introduction
3621
20.3.1.1 Features
3621
20.3.1.2 Unsupported RTC Features
3621
20.3.2 Integration
3622
20.3.2.1 RTC Connectivity Attributes
3622
20.3.2.2 RTC Clock and Reset Management
3623
20.3.2.3 RTC Pin List
3623
20.3.3 Functional Description
3624
20.3.3.1 Functional Block Diagram
3624
20.3.3.2 Clock Source
3624
20.3.3.3 Signal Descriptions
3625
20.3.3.4 Interrupt Support
3625
20.3.3.4.1 CPU Interrupts
3625
20.3.3.4.2 Interrupt Description
3625
20.3.3.5 Programming/Usage Guide
3627
20.3.3.5.1 Time/Calendar Data Format
3627
20.3.3.5.2 Register Access
3627
20.3.3.5.3 OCP MMR Spurious WRT Protection
3627
20.3.3.5.4 Reading the Timer/Calendar (TC) Registers
3628
20.3.3.5.5 Modifying the TC Registers
3629
20.3.3.5.6 Crystal Compensation
3630
20.3.3.6 Scratch Registers
3631
20.3.3.7 Power Management
3631
20.3.3.8 Power Management—System Level (PMIC Mode)
3631
20.3.4 Use Cases
3632
20.3.5 RTC Registers
3632
20.3.5.1 SECONDS_REG Register (offset = 0h) [reset = 0h]
3634
20.3.5.2 MINUTES_REG Register (offset = 4h) [reset = 0h]
3635
20.3.5.3 HOURS_REG Register (offset = 8h) [reset = 0h]
3636
20.3.5.4 DAYS_REG Register (offset = Ch) [reset = 1h]
3637
20.3.5.5 MONTHS_REG Register (offset = 10h) [reset = 1h]
3638
20.3.5.6 YEARS_REG Register (offset = 14h) [reset = 0h]
3639
20.3.5.7 WEEKS_REG Register (offset = 18h) [reset = 0h]
3640
20.3.5.8 ALARM_SECONDS_REG Register (offset = 20h) [reset = 0h]
3641
20.3.5.9 ALARM_MINUTES_REG Register (offset = 24h) [reset = 0h]
3642
20.3.5.10 ALARM_HOURS_REG Register (offset = 28h) [reset = 0h]
3643
20.3.5.11 ALARM_DAYS_REG Register (offset = 2Ch) [reset = 1h]
3644
20.3.5.12 ALARM_MONTHS_REG Register (offset = 30h) [reset = 1h]
3645
20.3.5.13 ALARM_YEARS_REG Register (offset = 34h) [reset = 0h]
3646
20.3.5.14 RTC_CTRL_REG Register (offset = 40h) [reset = 0h]
3647
20.3.5.15 RTC_STATUS_REG Register (offset = 44h) [reset = 0h]
3649
20.3.5.16 RTC_INTERRUPTS_REG Register (offset = 48h) [reset = 0h]
3650
20.3.5.17 RTC_COMP_LSB_REG Register (offset = 4Ch) [reset = 0h]
3651
20.3.5.18 RTC_COMP_MSB_REG Register (offset = 50h) [reset = 0h]
3652
20.3.5.19 RTC_OSC_REG Register (offset = 54h) [reset = 10h]
3653
20.3.5.20 RTC_SCRATCH0_REG Register (offset = 60h) [reset = 0h]
3654
20.3.5.21 RTC_SCRATCH1_REG Register (offset = 64h) [reset = 0h]
3655
20.3.5.22 RTC_SCRATCH2_REG Register (offset = 68h) [reset = 0h]
3656
20.3.5.23 KICK0R Register (offset = 6Ch) [reset = 0h]
3657
20.3.5.24 KICK1R Register (offset = 70h) [reset = 0h]
3658
20.3.5.25 RTC_REVISION Register (offset = 74h) [reset = 4EB00904h]
3659
20.3.5.26 RTC_SYSCONFIG Register (offset = 78h) [reset = 2h]
3660
20.3.5.27 RTC_IRQWAKEEN Register (offset = 7Ch) [reset = 0h]
3661
20.3.5.28 ALARM2_SECONDS_REG Register (offset = 80h) [reset = 0h]
3662
20.3.5.29 ALARM2_MINUTES_REG Register (offset = 84h) [reset = 0h]
3663
20.3.5.30 ALARM2_HOURS_REG Register (offset = 88h) [reset = 0h]
3664
20.3.5.31 ALARM2_DAYS_REG Register (offset = 8Ch) [reset = 1h]
3665
20.3.5.32 ALARM2_MONTHS_REG Register (offset = 90h) [reset = 1h]
3666
20.3.5.33 ALARM2_YEARS_REG Register (offset = 94h) [reset = 0h]
3667
20.3.5.34 RTC_PMIC Register (offset = 98h) [reset = 0h]
3668
20.3.5.35 RTC_DEBOUNCE Register (offset = 9Ch) [reset = 0h]
3669
20.4 WATCHDOG
3670
20.4.1 Introduction
3670
20.4.1.1 Features
3670
20.4.1.2 Unsupported Featres
3670
20.4.2 Integration
3671
20.4.2.1 Public WD Timer Connectivity Attributes
3671
20.4.2.2 Public WD Timer Clock and Reset Management
3671
20.4.3 Functional Description
3673
20.4.3.1 Power Management
3673
20.4.3.2 Interrupts
3673
20.4.3.3 General Watchdog Timer Operation
3673
20.4.3.4 Reset Context
3674
20.4.3.5 Overflow/Reset Generation
3674
20.4.3.6 Prescaler Value/Timer Reset Frequency
3674
20.4.3.7 Triggering a Timer Reload
3676
20.4.3.8 Start/Stop Sequence for Watchdog Timers (Using the WDT_WSPR Register)
3676
20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
3676
20.4.3.10 Watchdog Counter Register Access Restriction (WDT_WCRR Register)
3676
20.4.3.11 Watchdog Timer Interrupt Generation
3677
20.4.3.12 Watchdog Timers Under Emulation
3678
20.4.3.13 Accessing Watchdog Timer Registers
3678
20.4.3.14 Low-Level Programming Model
3679
20.4.3.14.1 Global Initialization
3679
20.4.3.14.2 Operational Mode Configuration
3679
20.4.4 Watchdog Registers
3680
20.4.4.1 WATCHDOG_TIMER Registers
3680
20.4.4.1.1 WDT_WIDR Register (offset = 0h) [reset = 0h]
3682
20.4.4.1.2 WDT_WDSC Register (offset = 10h) [reset = 10h]
3683
20.4.4.1.3 WDT_WDST Register (offset = 14h) [reset = 1h]
3684
20.4.4.1.4 WDT_WISR Register (offset = 18h) [reset = 0h]
3685
20.4.4.1.5 WDT_WIER Register (offset = 1Ch) [reset = 0h]
3686
20.4.4.1.6 WDT_WCLR Register (offset = 24h) [reset = 20h]
3687
20.4.4.1.7 WDT_WCRR Register (offset = 28h) [reset = 0h]
3688
20.4.4.1.8 WDT_WLDR Register (offset = 2Ch) [reset = 0h]
3689
20.4.4.1.9 WDT_WTGR Register (offset = 30h) [reset = 0h]
3690
20.4.4.1.10 WDT_WWPS Register (offset = 34h) [reset = 0h]
3691
20.4.4.1.11 WDT_WDLY Register (offset = 44h) [reset = 0h]
3692
20.4.4.1.12 WDT_WSPR Register (offset = 48h) [reset = 0h]
3693
20.4.4.1.13 WDT_WIRQSTATRAW Register (offset = 54h) [reset = 0h]
3694
20.4.4.1.14 WDT_WIRQSTAT Register (offset = 58h) [reset = 0h]
3695
20.4.4.1.15 WDT_WIRQENSET Register (offset = 5Ch) [reset = 0h]
3696
20.4.4.1.16 WDT_WIRQENCLR Register (offset = 60h) [reset = 0h]
3697
21 I2C
3698
21.1 Introduction
3699
21.1.1 I2C Features
3699
21.1.2 Unsupported I2C Features
3699
21.2 Integration
3700
21.2.1 I2C Connectivity Attributes
3700
21.2.2 I2C Clock and Reset Management
3701
21.2.3 I2C Pin List
3701
21.3 Functional Description
3702
21.3.1 Functional Block Diagram
3702
21.3.2 I2C Master/Slave Contoller Signals
3702
21.3.3 I2C Reset
3703
21.3.4 Data Validity
3703
21.3.5 START & STOP Conditions
3705
21.3.6 I2C Operation
3705
21.3.6.1 Serial Data Formats
3705
21.3.6.2 Master Transmitter
3706
21.3.6.3 Master Receiver
3706
21.3.6.4 Slave Transmitter
3706
21.3.6.5 Slave Receiver
3706
21.3.7 Arbitration
3707
21.3.8 I2C Clock Generation and I2C Clock Synchronization
3707
21.3.9 Prescaler (SCLK/ICLK)
3708
21.3.10 Noise Filter
3708
21.3.11 I2C Interrupts
3708
21.3.12 DMA Events
3709
21.3.13 Interrupt and DMA Events
3709
21.3.14 FIFO Management
3709
21.3.14.1 FIFO Interrupt Mode Operation
3709
21.3.14.2 FIFO Polling Mode Operation
3711
21.3.14.3 FIFO DMA Mode Operation
3711
21.3.14.4 Draining Feature
3714
21.3.15 How to Program I2C
3714
21.3.15.1 Module Configuration Before Enabling the Module
3714
21.3.15.2 Initialization Procedure
3714
21.3.15.3 Configure Slave Address and DATA Counter Registers
3714
21.3.15.4 Initiate a Transfer
3715
21.3.15.5 Receive Data
3715
21.3.15.6 Transmit Data
3715
21.4 I2C Registers
3716
21.4.1 I2C Registers
3716
21.4.1.1 I2C_REVNB_LO Register (offset = 00h) [reset = 0h]
3717
21.4.1.2 I2C_REVNB_HI Register (offset = 04h) [reset = 0h]
3718
21.4.1.3 I2C_SYSC Register (offset = 10h) [reset = 0h]
3719
21.4.1.4 I2C_IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
3721
21.4.1.5 I2C_IRQSTATUS Register (offset = 28h) [reset = 0h]
3727
21.4.1.6 I2C_IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
3729
21.4.1.7 I2C_IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
3731
21.4.1.8 I2C_WE Register (offset = 34h) [reset = 0h]
3733
21.4.1.9 I2C_DMARXENABLE_SET Register (offset = 38h) [reset = 0h]
3736
21.4.1.10 I2C_DMATXENABLE_SET Register (offset = 3Ch) [reset = 0h]
3737
21.4.1.11 I2C_DMARXENABLE_CLR Register (offset = 40h) [reset = 0h]
3738
21.4.1.12 I2C_DMATXENABLE_CLR Register (offset = 44h) [reset = 0h]
3739
21.4.1.13 I2C_DMARXWAKE_EN Register (offset = 48h) [reset = 0h]
3740
21.4.1.14 I2C_DMATXWAKE_EN Register (offset = 4Ch) [reset = 0h]
3742
21.4.1.15 I2C_SYSS Register (offset = 90h) [reset = 0h]
3744
21.4.1.16 I2C_BUF Register (offset = 94h) [reset = 0h]
3745
21.4.1.17 I2C_CNT Register (offset = 98h) [reset = 0h]
3747
21.4.1.18 I2C_DATA Register (offset = 9Ch) [reset = 0h]
3748
21.4.1.19 I2C_CON Register (offset = A4h) [reset = 0h]
3749
21.4.1.20 I2C_OA Register (offset = A8h) [reset = 0h]
3752
21.4.1.21 I2C_SA Register (offset = ACh) [reset = 0h]
3753
21.4.1.22 I2C_PSC Register (offset = B0h) [reset = 0h]
3754
21.4.1.23 I2C_SCLL Register (offset = B4h) [reset = 0h]
3755
21.4.1.24 I2C_SCLH Register (offset = B8h) [reset = 0h]
3756
21.4.1.25 I2C_SYSTEST Register (offset = BCh) [reset = 0h]
3757
21.4.1.26 I2C_BUFSTAT Register (offset = C0h) [reset = 0h]
3761
21.4.1.27 I2C_OA1 Register (offset = C4h) [reset = 0h]
3762
21.4.1.28 I2C_OA2 Register (offset = C8h) [reset = 0h]
3763
21.4.1.29 I2C_OA3 Register (offset = CCh) [reset = 0h]
3764
21.4.1.30 I2C_ACTOA Register (offset = D0h) [reset = 0h]
3765
21.4.1.31 I2C_SBLOCK Register (offset = D4h) [reset = 0h]
3766
22 Multichannel Audio Serial Port (McASP)
3768
22.1 Introduction
3769
22.1.1 Purpose of the Peripheral
3769
22.1.2 Features
3769
22.1.3 Protocols Supported
3769
22.1.4 Unsupported McASP Features
3770
22.2 Integration
3771
22.2.1 McASP Connectivity Attributes
3771
22.2.2 McASP Clock and Reset Management
3772
22.2.3 McASP Pin List
3772
22.3 Functional Description
3773
22.3.1 Overview
3773
22.3.2 Functional Block Diagram
3774
22.3.2.1 System Level Connections
3775
22.3.3 Industry Standard Compliance Statement
3777
22.3.3.1 TDM Format
3777
22.3.3.1.1 TDM Format
3777
22.3.3.1.2 Inter-Integrated Sound (I2S) Format
3778
22.3.3.2 S/PDIF Coding Format
3779
22.3.3.2.1 Biphase-Mark Code (BMC)
3779
22.3.3.2.2 Subframe Format
3780
22.3.3.2.3 Frame Format
3781
22.3.4 Definition of Terms
3781
22.3.5 Clock and Frame Sync Generators
3783
22.3.5.1 Transmit Clock
3784
22.3.5.2 Receive Clock
3785
22.3.5.3 Frame Sync Generator
3786
22.3.5.4 Clocking Examples
3787
22.3.6 Signal Descriptions
3787
22.3.7 Pin Multiplexing
3787
22.3.8 Transfer Modes
3788
22.3.8.1 Burst Transfer Mode
3788
22.3.8.2 Time-Division Multiplexed (TDM) Transfer Mode
3789
22.3.8.2.1 TDM Time Slots
3790
22.3.8.2.2 Special 384 Slot TDM Mode for Connection to External DIR
3791
22.3.8.3 Digital Audio Interface Transmit (DIT) Transfer Mode
3791
22.3.8.3.1 Transmit DIT Encoding
3791
22.3.8.3.2 Transmit DIT Clock and Frame Sync Generation
3792
22.3.8.3.3 DIT Channel Status and User Data Register Files
3793
22.3.9 General Architecture
3795
22.3.9.1 Serializers
3795
22.3.9.2 Format Unit
3795
22.3.9.3 State Machine
3797
22.3.9.4 TDM Sequencer
3797
22.3.9.5 Clock Check Circuit
3797
22.3.9.6 Pin Function Control
3798
22.3.9.6.1 McASP Pin Control-Transmit and Receive
3798
22.3.10 Operation
3799
22.3.10.1 Data Transmission and Reception
3799
22.3.10.1.1 Data Ready Status and Event/Interrupt Generation
3799
22.3.10.1.2 Transfers Through the Data Port (DAT)
3802
22.3.10.1.3 Transfers Through the Configuration Bus (CFG)
3802
22.3.10.1.4 Using the CPU for McASP Servicing
3802
22.3.10.2 McASP Audio FIFO (AFIFO)
3803
22.3.10.2.1 AFIFO Data Transmission
3803
22.3.10.2.2 AFIFO Data Reception
3804
22.3.10.2.3 Arbitration Between Transmit and Receive DMA Requests
3804
22.3.10.3 Formatter
3805
22.3.10.3.1 Transmit Bit Stream Data Alignment
3805
22.3.10.3.2 Receive Bit Stream Data Alignment
3807
22.3.10.4 Error Handling and Management
3809
22.3.10.4.1 Unexpected Frame Sync Error
3809
22.3.10.4.2 Buffer Underrun Error - Transmitter
3809
22.3.10.4.3 Buffer Overrun Error - Receiver
3810
22.3.10.4.4 DMA Error - Transmitter
3810
22.3.10.4.5 DMA Error - Receiver
3810
22.3.10.4.6 Clock Failure Detection
3811
22.3.10.5 Loopback Modes
3815
22.3.10.5.1 Loopback Mode Configurations
3816
22.3.11 Reset Considerations
3816
22.3.11.1 Software Reset Considerations
3816
22.3.11.2 Hardware Reset Considerations
3816
22.3.12 Setup and Initialization
3816
22.3.12.1 Considerations When Using a McASP
3816
22.3.12.1.1 Clocks
3816
22.3.12.1.2 Data Pins
3816
22.3.12.1.3 Data Format
3817
22.3.12.1.4 Data Transfers
3817
22.3.12.2 Transmit/Receive Section Initialization
3817
22.3.12.3 Separate Transmit and Receive Initialization
3820
22.3.12.4 Importance of Reading Back GBLCTL
3820
22.3.12.5 Synchronous Transmit and Receive Operation (ASYNC = 0)
3820
22.3.12.6 Asynchronous Transmit and Receive Operation (ASYNC = 1)
3820
22.3.13 Interrupts
3821
22.3.13.1 Interrupt Multiplexing
3821
22.3.13.2 Transmit Data Ready Interrupt
3821
22.3.13.3 Receive Data Ready Interrupt
3821
22.3.13.4 Error Interrupts
3821
22.3.13.5 Audio Mute (AMUTE) Function
3822
22.3.13.6 Multiple Interrupts
3823
22.3.14 EDMA Event Support
3823
22.3.14.1 EDMA Events
3823
22.3.14.2 Using the DMA for McASP Servicing
3823
22.3.15 Power Management
3825
22.3.16 Emulation Considerations
3825
22.4 McASP Registers
3826
22.4.1 McASP CFG Registers
3826
22.4.1.1 Revision Identification Register (REV)
3828
22.4.1.2 Power Idle SYSCONFIG Register (PWRIDLESYSCONFIG)
3829
22.4.1.3 Pin Function Register (PFUNC)
3830
22.4.1.4 Pin Direction Register (PDIR)
3832
22.4.1.5 Pin Data Output Register (PDOUT)
3834
22.4.1.6 Pin Data Input Register (PDIN)
3836
22.4.1.7 Pin Data Set Register (PDSET)
3838
22.4.1.8 Pin Data Clear Register (PDCLR)
3840
22.4.1.9 Global Control Register (GBLCTL)
3842
22.4.1.10 Audio Mute Control Register (AMUTE)
3844
22.4.1.11 Digital Loopback Control Register (DLBCTL)
3846
22.4.1.12 Digital Mode Control Register (DITCTL)
3847
22.4.1.13 Receiver Global Control Register (RGBLCTL)
3848
22.4.1.14 Receive Format Unit Bit Mask Register (RMASK)
3849
22.4.1.15 Receive Bit Stream Format Register (RFMT)
3850
22.4.1.16 Receive Frame Sync Control Register (AFSRCTL)
3852
22.4.1.17 Receive Clock Control Register (ACLKRCTL)
3853
22.4.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL)
3854
22.4.1.19 Receive TDM Time Slot Register (RTDM)
3855
22.4.1.20 Receiver Interrupt Control Register (RINTCTL)
3856
22.4.1.21 Receiver Status Register (RSTAT)
3857
22.4.1.22 Current Receive TDM Time Slot Registers (RSLOT)
3858
22.4.1.23 Receive Clock Check Control Register (RCLKCHK)
3859
22.4.1.24 Receiver DMA Event Control Register (REVTCTL)
3860
22.4.1.25 Transmitter Global Control Register (XGBLCTL)
3861
22.4.1.26 Transmit Format Unit Bit Mask Register (XMASK)
3862
22.4.1.27 Transmit Bit Stream Format Register (XFMT)
3863
22.4.1.28 Transmit Frame Sync Control Register (AFSXCTL)
3865
22.4.1.29 Transmit Clock Control Register (ACLKXCTL)
3866
22.4.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL)
3867
22.4.1.31 Transmit TDM Time Slot Register (XTDM)
3868
22.4.1.32 Transmitter Interrupt Control Register (XINTCTL)
3869
22.4.1.33 Transmitter Status Register (XSTAT)
3870
22.4.1.34 Current Transmit TDM Time Slot Register (XSLOT)
3871
22.4.1.35 Transmit Clock Check Control Register (XCLKCHK)
3872
22.4.1.36 Transmitter DMA Event Control Register (XEVTCTL)
3873
22.4.1.37 Serializer Control Registers (SRCTLn)
3874
22.4.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
3875
22.4.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
3875
22.4.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
3875
22.4.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
3875
22.4.1.42 Transmit Buffer Registers (XBUFn)
3876
22.4.1.43 Receive Buffer Registers (RBUFn)
3876
22.4.1.44 Write FIFO Control Register (WFIFOCTL)
3877
22.4.1.45 Write FIFO Status Register (WFIFOSTS)
3878
22.4.1.46 Read FIFO Control Register (RFIFOCTL)
3879
22.4.1.47 Read FIFO Status Register (RFIFOSTS)
3880
22.4.2 McASP Data Port Registers
3880
23 Controller Area Network (CAN)
3881
23.1 Introduction
3882
23.1.1 DCAN Features
3882
23.1.2 Unsupported DCAN Features
3882
23.2 Integration
3883
23.2.1 DCAN Connectivity Attributes
3883
23.2.2 DCAN Clock and Reset Management
3884
23.2.3 DCAN Pin List
3884
23.3 Functional Description
3885
23.3.1 CAN Core
3885
23.3.2 Message Handler
3886
23.3.3 Message RAM
3886
23.3.4 Message RAM Interface
3886
23.3.5 Registers and Message Object Access
3886
23.3.6 Module Interface
3886
23.3.7 Dual Clock Source
3886
23.3.8 CAN Operation
3887
23.3.8.1 CAN Module Initialization
3887
23.3.8.1.1 Configuration of CAN Bit Timing
3887
23.3.8.1.2 Configuration of Message Objects
3889
23.3.8.1.3 DCAN RAM Hardware Initialization
3889
23.3.8.2 CAN Message Transfer (Normal Operation)
3889
23.3.8.2.1 Automatic Retransmission
3890
23.3.8.2.2 Auto-Bus-On
3890
23.3.8.3 Test Modes
3890
23.3.8.3.1 Silent Mode
3890
23.3.8.3.2 Loopback Mode
3891
23.3.8.3.3 External Loopback Mode
3892
23.3.8.3.4 Loopback Mode Combined With Silent Mode
3892
23.3.8.3.5 Software Control of CAN_TX pin
3893
23.3.9 Dual Clock Source
3893
23.3.10 Interrupt Functionality
3894
23.3.10.1 Message Object Interrupts
3894
23.3.10.2 Status Change Interrupts
3894
23.3.10.3 Error Interrupts
3895
23.3.11 Local Power-Down Mode
3896
23.3.11.1 Entering Local Power-Down Mode
3896
23.3.11.2 Wakeup From Local Power Down
3896
23.3.12 Parity Check Mechanism
3898
23.3.12.1 Behavior on Parity Error
3898
23.3.12.2 Parity Testing
3898
23.3.13 Debug/Suspend Mode
3899
23.3.14 Configuration of Message Objects
3899
23.3.14.1 Configuration of a Transmit Object for Data Frames
3900
23.3.14.2 Configuration of a Transmit Object for Remote Frames
3900
23.3.14.3 Configuration of a Single Receive Object for Data Frames
3900
23.3.14.4 Configuration of a Single Receive Object for Remote Frames
3901
23.3.14.5 Configuration of a FIFO Buffer
3901
23.3.15 Message Handling
3902
23.3.15.1 Message Handler Overview
3902
23.3.15.2 Receive/Transmit Priority
3902
23.3.15.3 Transmission of Messages in Event-Driven CAN Communication
3902
23.3.15.4 Updating a Transmit Object
3903
23.3.15.5 Changing a Transmit Object
3903
23.3.15.6 Acceptance Filtering of Received Messages
3904
23.3.15.7 Reception of Data Frames
3904
23.3.15.8 Reception of Remote Frames
3904
23.3.15.9 Reading Received Messages
3904
23.3.15.10 Requesting New Data for a Receive Object
3905
23.3.15.11 Storing Received Messages in FIFO Buffers
3905
23.3.15.12 Reading From a FIFO Buffer
3905
23.3.16 CAN Bit Timing
3907
23.3.16.1 Bit Time and Bit Rate
3907
23.3.16.1.1 Synchronization Segment
3908
23.3.16.1.2 Propagation Time Segment
3908
23.3.16.1.3 Phase Buffer Segments and Synchronization
3909
23.3.16.1.4 Oscillator Tolerance Range
3911
23.3.16.2 DCAN Bit Timing Registers
3912
23.3.16.2.1 Calculation of the Bit Timing Parameters
3913
23.3.16.2.2 Example for Bit Timing at High Baud Rate
3913
23.3.16.2.3 Example for Bit Timing at Low Baud Rate
3914
23.3.17 Message Interface Register Sets
3915
23.3.17.1 Message Interface Register Sets 1 and 2
3915
23.3.17.2 IF3 Register Set
3916
23.3.18 Message RAM
3917
23.3.18.1 Structure of Message Objects
3918
23.3.18.2 Addressing Message Objects in RAM
3920
23.3.18.3 Message RAM Representation in Debug/Suspend Mode
3921
23.3.18.4 Message RAM Representation in Direct Access Mode
3921
23.3.19 GIO Support
3922
23.4 DCAN Registers
3922
23.4.1 CTL Register (offset = 00h) [reset = 1401h]
3924
23.4.2 ES Register (offset = 04h) [reset = 6Fh]
3927
23.4.3 ERRC Register (offset = 08h) [reset = 0h]
3929
23.4.4 BTR Register (offset = 0Ch) [reset = 2301h]
3930
23.4.5 INT Register (offset = 10h) [reset = 0h]
3931
23.4.6 TEST Register (offset = 14h) [reset = 0h]
3932
23.4.7 PERR Register (offset = 1Ch) [reset = 0h]
3933
23.4.8 ABOTR Register (offset = 80h) [reset = 0h]
3934
23.4.9 TXRQ_X Register (offset = 84h) [reset = 0h]
3935
23.4.10 TXRQ12 Register (offset = 88h) [reset = 0h]
3936
23.4.11 TXRQ34 Register (offset = 8Ch) [reset = 0h]
3937
23.4.12 TXRQ56 Register (offset = 90h) [reset = 0h]
3938
23.4.13 TXRQ78 Register (offset = 94h) [reset = 0h]
3939
23.4.14 NWDAT_X Register (offset = 98h) [reset = 0h]
3940
23.4.15 NWDAT12 Register (offset = 9Ch) [reset = 0h]
3941
23.4.16 NWDAT34 Register (offset = A0h) [reset = 0h]
3942
23.4.17 NWDAT56 Register (offset = A4h) [reset = 0h]
3943
23.4.18 NWDAT78 Register (offset = A8h) [reset = 0h]
3944
23.4.19 INTPND_X Register (offset = ACh) [reset = 0h]
3945
23.4.20 INTPND12 Register (offset = B0h) [reset = 0h]
3946
23.4.21 INTPND34 Register (offset = B4h) [reset = 0h]
3947
23.4.22 INTPND56 Register (offset = B8h) [reset = 0h]
3948
23.4.23 INTPND78 Register (offset = BCh) [reset = 0h]
3949
23.4.24 MSGVAL_X Register (offset = C0h) [reset = 0h]
3950
23.4.25 MSGVAL12 Register (offset = C4h) [reset = 0h]
3951
23.4.26 MSGVAL34 Register (offset = C8h) [reset = 0h]
3952
23.4.27 MSGVAL56 Register (offset = CCh) [reset = 0h]
3953
23.4.28 MSGVAL78 Register (offset = D0h) [reset = 0h]
3954
23.4.29 INTMUX12 Register (offset = D8h) [reset = 0h]
3955
23.4.30 INTMUX34 Register (offset = DCh) [reset = 0h]
3956
23.4.31 INTMUX56 Register (offset = E0h) [reset = 0h]
3957
23.4.32 INTMUX78 Register (offset = E4h) [reset = 0h]
3958
23.4.33 IF1CMD Register (offset = 100h) [reset = 0h]
3959
23.4.34 IF1MSK Register (offset = 104h) [reset = E0000000h]
3962
23.4.35 IF1ARB Register (offset = 108h) [reset = 0h]
3963
23.4.36 IF1MCTL Register (offset = 10Ch) [reset = 0h]
3964
23.4.37 IF1DATA Register (offset = 110h) [reset = 0h]
3966
23.4.38 IF1DATB Register (offset = 114h) [reset = 0h]
3967
23.4.39 IF2CMD Register (offset = 120h) [reset = 0h]
3968
23.4.40 IF2MSK Register (offset = 124h) [reset = E0000000h]
3971
23.4.41 IF2ARB Register (offset = 128h) [reset = 0h]
3972
23.4.42 IF2MCTL Register (offset = 12Ch) [reset = 0h]
3973
23.4.43 IF2DATA Register (offset = 130h) [reset = 0h]
3975
23.4.44 IF2DATB Register (offset = 134h) [reset = 0h]
3976
23.4.45 IF3OBS Register (offset = 140h) [reset = 0h]
3977
23.4.46 IF3MSK Register (offset = 144h) [reset = E0000000h]
3979
23.4.47 IF3ARB Register (offset = 148h) [reset = 0h]
3980
23.4.48 IF3MCTL Register (offset = 14Ch) [reset = 0h]
3981
23.4.49 IF3DATA Register (offset = 150h) [reset = 0h]
3983
23.4.50 IF3DATB Register (offset = 154h) [reset = 0h]
3984
23.4.51 IF3UPD12 Register (offset = 160h) [reset = 0h]
3985
23.4.52 IF3UPD34 Register (offset = 164h) [reset = 0h]
3986
23.4.53 IF3UPD56 Register (offset = 168h) [reset = 0h]
3987
23.4.54 IF3UPD78 Register (offset = 16Ch) [reset = 0h]
3988
23.4.55 TIOC Register (offset = 1E0h) [reset = 0h]
3989
23.4.56 RIOC Register (offset = 1E4h) [reset = 0h]
3991
24 Multichannel Serial Port Interface (McSPI)
3993
24.1 Introduction
3994
24.1.1 McSPI Features
3994
24.1.2 Unsupported McSPI Features
3994
24.2 Integration
3995
24.2.1 McSPI Connectivity Attributes
3996
24.2.2 McSPI Clock and Reset Management
3996
24.2.3 McSPI Pin List
3996
24.3 Functional Description
3997
24.3.1 SPI Transmission
3997
24.3.1.1 Two Data Pins Interface Mode
3998
24.3.1.2 Single Data Pin Interface Mode
3998
24.3.1.2.1 Example With a Receive-Only Slave
3999
24.3.1.2.2 Example With a Transmit-Only Slave
3999
24.3.1.3 Transfer Formats
4000
24.3.1.3.1 Programmable Word Length
4000
24.3.1.3.2 Programmable SPI Enable Generation
4000
24.3.1.3.3 Programmable SPI Enable (SPIEN)
4000
24.3.1.3.4 Programmable SPI Clock (SPICLK)
4000
24.3.1.3.5 Bit Rate
4000
24.3.1.3.6 Polarity and Phase
4001
24.3.1.3.7 Transfer Format With PHA = 0
4002
24.3.1.3.8 Transfer Format With PHA = 1
4003
24.3.2 Master Mode
4004
24.3.2.1 Dedicated Resources Per Channel
4004
24.3.2.2 Interrupt Events in Master Mode
4005
24.3.2.2.1 TX_empty
4005
24.3.2.2.2 TX_underflow
4005
24.3.2.2.3 RX_ full
4005
24.3.2.2.4 End of Word Count
4005
24.3.2.3 Master Transmit and Receive Mode
4006
24.3.2.4 Master Transmit-Only Mode
4006
24.3.2.5 Master Receive-Only Mode
4007
24.3.2.6 Single-Channel Master Mode
4007
24.3.2.6.1 Programming Tips When Switching to Another Channel
4007
24.3.2.6.2 Keep SPIEN Active Mode (Force SPIEN)
4007
24.3.2.6.3 Turbo Mode
4009
24.3.2.7 Start Bit Mode
4009
24.3.2.8 Chip-Select Timing Control
4011
24.3.2.9 Clock Ratio Granularity
4013
24.3.2.10 FIFO Buffer Management
4014
24.3.2.10.1 Split FIFO
4014
24.3.2.10.2 Buffer Almost Full
4018
24.3.2.10.3 Buffer Almost Empty
4019
24.3.2.10.4 End of Transfer Management
4019
24.3.2.10.5 Multiple SPI Word Access
4020
24.3.2.11 First SPI Word Delayed
4020
24.3.2.12 3- or 4-Pin Mode
4021
24.3.3 Slave Mode
4022
24.3.3.1 Dedicated Resources
4022
24.3.3.2 Interrupt Events in Slave Mode
4023
24.3.3.2.1 TX_EMPTY
4023
24.3.3.2.2 TX_UNDERFLOW
4024
24.3.3.2.3 RX_FULL
4024
24.3.3.2.4 RX_OVERFLOW
4024
24.3.3.2.5 End of Word Count
4024
24.3.3.3 Slave Transmit-and-Receive Mode
4024
24.3.3.4 Slave Receive-Only Mode
4025
24.3.3.5 Slave Transmit-Only Mode
4026
24.3.4 Interrupts
4026
24.3.4.1 Interrupt-Driven Operation
4027
24.3.4.2 Polling
4027
24.3.5 DMA Requests
4027
24.3.5.1 FIFO Buffer Disabled
4027
24.3.5.2 FIFO Buffer Enabled
4028
24.3.5.3 DMA 256-Bit Aligned Addresses
4028
24.3.6 Emulation Mode
4028
24.3.7 Power Saving Management
4029
24.3.7.1 Normal Mode
4029
24.3.7.2 Idle Mode
4029
24.3.7.2.1 Transitions from Normal Mode to Smart-Idle Mode
4029
24.3.7.2.2 Transition From Smart-Idle Mode to Normal mode
4030
24.3.7.2.3 Force-Idle Mode
4030
24.3.8 System Test Mode
4030
24.3.9 Reset
4030
24.3.9.1 Internal Reset Monitoring
4030
24.3.9.2 Reset Values of Registers
4031
24.3.10 Access to Data Registers
4031
24.3.11 Programming Aid
4031
24.3.11.1 Module Initialization
4031
24.3.11.2 Common Transfer Sequence
4031
24.3.11.3 Main Program
4032
24.3.12 Interrupt and DMA Events
4032
24.4 McSPI Registers
4032
24.4.1 SPI Registers
4032
24.4.1.1 McSPI Revision Register (MCSPI_REVISION)
4034
24.4.1.2 McSPI System Configuration Register (MCSPI_SYSCONFIG)
4035
24.4.1.3 McSPI System Status Register (MCSPI_SYSSTATUS)
4036
24.4.1.4 McSPI Interrupt Status Register (MCSPI_IRQSTATUS)
4037
24.4.1.5 McSPI Interrupt Enable Register (MCSPI_IRQENABLE)
4040
24.4.1.6 McSPI System Register (MCSPI_SYST)
4042
24.4.1.7 McSPI Module Control Register (MCSPI_MODULCTRL)
4044
24.4.1.8 McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF)
4046
24.4.1.9 McSPI Channel (i) Status Register (MCSPI_CH(i)STAT)
4050
24.4.1.10 McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL)
4051
24.4.1.11 McSPI Channel (i) Transmit Register (MCSPI_TX(i))
4052
24.4.1.12 McSPI Channel (i) Receive Register (MCSPI_RX(i))
4052
24.4.1.13 McSPI Transfer Levels Register (MCSPI_XFERLEVEL)
4053
24.4.1.14 McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX)
4054
24.4.1.15 McSPI DMA Address Aligned FIFO Receiver Register (MCSPI_DAFRX)
4055
25 General-Purpose Input/Output
4056
25.1 Introduction
4057
25.1.1 Purpose of the Peripheral
4057
25.1.2 GPIO Features
4057
25.1.3 Unsupported GPIO Features
4057
25.2 Integration
4058
25.2.1 GPIO Connectivity Attributes
4058
25.2.2 GPIO Clock and Reset Management
4059
25.2.3 GPIO Pin List
4060
25.3 Functional Description
4061
25.3.1 Operating Modes
4061
25.3.2 Clocking and Reset Strategy
4061
25.3.2.1 Clocks
4061
25.3.2.2 Clocks, Gating and Active Edge Definitions
4061
25.3.2.3 Sleep Mode Request and Acknowledge
4062
25.3.2.4 Reset
4062
25.3.3 Interrupt Features
4062
25.3.3.1 Functional Description
4062
25.3.3.2 Synchronous Path: Interrupt Request Generation
4063
25.3.3.3 Interrupt Line Release
4064
25.3.4 General-Purpose Interface Basic Programming Model
4064
25.3.4.1 Power Saving by Grouping the Edge/Level Detection
4064
25.3.4.2 Set and Clear Instructions
4064
25.3.4.2.1 Clear Instruction
4065
25.3.4.2.2 Set Instruction
4065
25.3.4.3 Data Input (Capture)/Output (Drive)
4066
25.3.4.4 Debouncing Time
4066
25.3.4.5 GPIO as a Keyboard Interface
4067
25.4 GPIO Registers
4068
25.4.1 GPIO Registers
4068
25.4.1.1 GPIO_REVISION Register (offset = 0h) [reset = 50600801h]
4069
25.4.1.2 GPIO_SYSCONFIG Register (offset = 10h) [reset = 0h]
4070
25.4.1.3 GPIO_EOI Register (offset = 20h) [reset = 0h]
4071
25.4.1.4 GPIO_IRQSTATUS_RAW_0 Register (offset = 24h) [reset = 0h]
4072
25.4.1.5 GPIO_IRQSTATUS_RAW_1 Register (offset = 28h) [reset = 0h]
4073
25.4.1.6 GPIO_IRQSTATUS_0 Register (offset = 2Ch) [reset = 0h]
4074
25.4.1.7 GPIO_IRQSTATUS_1 Register (offset = 30h) [reset = 0h]
4075
25.4.1.8 GPIO_IRQSTATUS_SET_0 Register (offset = 34h) [reset = 0h]
4076
25.4.1.9 GPIO_IRQSTATUS_SET_1 Register (offset = 38h) [reset = 0h]
4077
25.4.1.10 GPIO_IRQSTATUS_CLR_0 Register (offset = 3Ch) [reset = 0h]
4078
25.4.1.11 GPIO_IRQSTATUS_CLR_1 Register (offset = 40h) [reset = 0h]
4079
25.4.1.12 GPIO_IRQWAKEN_0 Register (offset = 44h) [reset = 0h]
4080
25.4.1.13 GPIO_IRQWAKEN_1 Register (offset = 48h) [reset = 0h]
4081
25.4.1.14 GPIO_SYSSTATUS Register (offset = 114h) [reset = 0h]
4082
25.4.1.15 GPIO_CTRL Register (offset = 130h) [reset = 0h]
4083
25.4.1.16 GPIO_OE Register (offset = 134h) [reset = FFFFFFFFh]
4084
25.4.1.17 GPIO_DATAIN Register (offset = 138h) [reset = 0h]
4085
25.4.1.18 GPIO_DATAOUT Register (offset = 13Ch) [reset = 0h]
4086
25.4.1.19 GPIO_LEVELDETECT0 Register (offset = 140h) [reset = 0h]
4087
25.4.1.20 GPIO_LEVELDETECT1 Register (offset = 144h) [reset = 0h]
4088
25.4.1.21 GPIO_RISINGDETECT Register (offset = 148h) [reset = 0h]
4089
25.4.1.22 GPIO_FALLINGDETECT Register (offset = 14Ch) [reset = 0h]
4090
25.4.1.23 GPIO_DEBOUNCENABLE Register (offset = 150h) [reset = 0h]
4091
25.4.1.24 GPIO_DEBOUNCINGTIME Register (offset = 154h) [reset = 0h]
4092
25.4.1.25 GPIO_CLEARDATAOUT Register (offset = 190h) [reset = 0h]
4093
25.4.1.26 GPIO_SETDATAOUT Register (offset = 194h) [reset = 0h]
4094
26 Initialization
4095
26.1 Functional Description
4096
26.1.1 Architecture
4096
26.1.2 Functionality
4096
26.1.3 Memory Map
4097
26.1.3.1 Public ROM Memory Map
4097
26.1.3.2 Public RAM Memory Map
4100
26.1.4 Start-up and Configuration
4101
26.1.4.1 ROM Code Start-up
4101
26.1.4.2 CPU State at Public Startup
4102
26.1.4.3 Clocking Configuration
4102
26.1.5 Booting
4103
26.1.5.1 Overview
4103
26.1.5.2 Device List
4105
26.1.5.2.1 SYSBOOT Configuration Pins
4105
26.1.6 Fast External Booting
4112
26.1.6.1 Overview
4112
26.1.6.2 External Booting
4112
26.1.7 Memory Booting
4114
26.1.7.1 Overview
4114
26.1.7.2 XIP Memory
4115
26.1.7.2.1 XIP Initialization and Detection
4115
26.1.7.2.2 Pins Used
4117
26.1.7.2.3 Sysboot Pins
4118
26.1.7.3 Image Shadowing for Non-XIP Memories
4118
26.1.7.3.1 Shadowing on GP Device
4118
26.1.7.4 NAND
4118
26.1.7.4.1 Features
4118
26.1.7.4.2 Initialization and Detection
4119
26.1.7.5 MMC / SD Cards
4129
26.1.7.5.1 Overview
4129
26.1.7.5.2 System Interconnection
4129
26.1.7.5.3 Booting Procedure
4130
26.1.7.5.4 Initialization and Detection
4130
26.1.7.5.5 MMC/SD Read Sector Procedure in Raw Mode
4131
26.1.7.5.6 MMC/SD Read Sector Procedure in FAT Mode
4132
26.1.7.5.7 FAT File system
4133
26.1.7.5.8 Pins Used
4141
26.1.7.6 SPI
4141
26.1.7.6.1 Features
4142
26.1.7.6.2 Initialization and Detection
4142
26.1.7.6.3 SPI Read Sector Procedure
4142
26.1.7.6.4 Pins Used
4142
26.1.7.7 Blocks and Sectors Search Summary
4142
26.1.8 Peripheral Booting
4143
26.1.8.1 Overview
4143
26.1.8.2 Boot Image Location and Size
4143
26.1.8.3 Peripheral Boot Procedure Overview
4143
26.1.8.4 EMAC Boot Procedure
4144
26.1.8.4.1 Device Initialization
4144
26.1.8.4.2 BOOTP (RFC 951)
4144
26.1.8.4.3 TFTP (RFC 1350)
4145
26.1.8.4.4 Pins Used
4146
26.1.8.4.5 SYSBOOT Pins
4147
26.1.8.5 UART Boot Procedure
4147
26.1.8.5.1 Device Initialization
4147
26.1.8.5.2 Boot Image Download
4147
26.1.8.5.3 Pins Used
4147
26.1.8.6 USB Boot Procedure
4147
26.1.8.6.1 Device Initialization
4147
26.1.8.6.2 Image Download Procedure
4149
26.1.8.6.3 Pins Used
4149
26.1.8.7 ASIC ID structure
4149
26.1.9 Image Format
4149
26.1.9.1 Overview
4149
26.1.9.2 Image Format for GP Device
4150
26.1.10 Code Execution
4150
26.1.10.1 Overview
4150
26.1.10.2 Execution
4151
26.1.11 Wakeup
4152
26.1.11.1 Overview
4152
26.1.11.2 Wakeup Booting by ROM Code
4152
26.1.12 Tracing
4153
27 Debug Subsystem
4156
27.1 Functional Description
4157
27.1.1 Debug Suspend Support for Peripherals
4157
27.1.1.1 Debug Subsystem Registers
4157
A Revision History
4159
Other manuals for Texas Instruments AM335 Series
Quick Start Guide
6 pages
Design Guide
39 pages
5
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Texas Instruments AM335 Series Specifications
General
Brand
Texas Instruments
Model
AM335 Series
Category
Computer Hardware
Language
English
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