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EDMA3 Registers
Figure 11-48. QDMA Channel Queue Number Register (QDMAQNUM)
31 30 28 27 26 24 23 22 20 19 18 16
Rsvd E7 Rsvd E6 Rsvd E5 Rsvd E4
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
15 14 12 11 10 8 7 6 4 3 2 0
Rsvd E3 Rsvd E2 Rsvd E1 Rsvd E0
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-33. QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
Bit Field Value Description
31-15 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
14-0 En 0-7h QDMA queue number. Contains the event queue number to be used for the corresponding QDMA
channel.
0 Event n is queued on Q0.
1h Event n is queued on Q1.
2h Event n is queued on Q2.
3h Event n is queued on Q3.
4h-7h Reserved.
949
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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