EMIF
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Table 7-123. PWR_MGMT_CTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
7-4 reg_sr_tim R/W 0h Power Management timer for Self Refresh.
The EMIF will put the external SDRAM in Self Refresh mode after
the EMIF is idle for these number of DDR clock cycles and if
reg_lp_mode field is set to 2.
Set to 0 to immediately enter Self Refresh mode.
Set to 1 for 16 clocks.
Set to 2 for 32 clocks.
Set to 3 for 64 clocks.
Set to 4 for 128 clocks.
Set to 5 for 256 clocks.
Set to 6 for 512 clocks.
Set to 7 for 1024 clocks.
Set to 8 for 2048 clocks.
Set to 9 for 4096 clocks.
Set to 10 for 8192 clocks.
Set to 11 for 16384 clocks.
Set to 12 for 32768 clocks.
Set to 13 for 65536 clocks.
Set to 14 for 131072 clocks.
Set to 15 for 262144 clocks.
Note: After updating this field, at least one dummy read access to
SDRAM is required for the new value to take affect.
3-0 reg_cs_tim R/W 0h Power Management timer for Clock Stop.
The EMIF will put the external SDRAM in Clock Stop mode after the
EMIF is idle for these number of DDR clock cycles and if
reg_lp_mode field is set to 1.
Set to 0 to immediately enter Clock Stop mode.
Set to 1 for 16 clocks.
Set to 2 for 32 clocks.
Set to 3 for 64 clocks.
Set to 4 for 128 clocks.
Set to 5 for 256 clocks.
Set to 6 for 512 clocks.
Set to 7 for 1024 clocks.
Set to 8 for 2048 clocks.
Set to 9 for 4096 clocks.
Set to 10 for 8192 clocks.
Set to 11 for 16384 clocks.
Set to 12 for 32768 clocks.
Set to 13 for 65536 clocks.
Set to 14 for 131072 clocks.
Set to 15 for 262144 clocks.
Note: After updating this field, at least one dummy read access to
SDRAM is required for the new value to take affect.
438
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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