I2C Registers
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Table 21-24. I2C_BUF Register Field Descriptions (continued)
Bit Field Type Reset Description
7 XDMA_EN R/W 0h Transmit DMA channel enable.
When this bit is set to 1, the transmit DMA channel is enabled and
the transmit data ready status (I2C_IRQSTATUS_RAW: XRDY) bit is
forced to 0 by the core.
Value after reset is low.
0x0 = Transmit DMA channel disabled
0x1 = Transmit DMA channel enabled
6 TXFIFO_CLR R/W 0h Transmit FIFO clear.
When set, transmit FIFO is cleared (hardware reset for TX FIFO).
This bit is automatically reset by the hardware.
During reads, it always returns 0.
Value after reset is low.
0x0 = Normal mode
0x1 = Tx FIFO is reset
5-0 TXTRSH R/W 0h Threshold value for FIFO buffer in TX mode.
The Transmit Threshold value is used to specify the trigger level for
data transfers.
The value is specified from the OCP point of view.
Value after reset is 00h Note
1: programmed threshold cannot exceed the actual depth of the
FIFO.
Note
2: the threshold must not be changed while a transfer is in progress
(after STT was configured or after the module was addressed as a
slave).
0x0 = Transmit Threshold value = 1
0x1 = Transmit Threshold value = 2
0x3F = Transmit Threshold value = 64
3746
I2C SPRUH73H–October 2011–Revised April 2013
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